forked from OSchip/llvm-project
[GlobalISel] Combine shr(shl x, c1), c2 to G_SBFX/G_UBFX
Reviewed By: foad Differential Revision: https://reviews.llvm.org/D107330
This commit is contained in:
Dominik Montada
parent
a82c7476a7
commit
cc947e29ea
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@ -541,6 +541,10 @@ public:
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bool matchBitfieldExtractFromAnd(
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MachineInstr &MI, std::function<void(MachineIRBuilder &)> &MatchInfo);
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/// Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width
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bool matchBitfieldExtractFromShr(
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MachineInstr &MI, std::function<void(MachineIRBuilder &)> &MatchInfo);
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/// Reassociate pointer calculations with G_ADD involved, to allow better
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/// addressing mode usage.
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bool matchReassocPtrAdd(MachineInstr &MI,
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@ -652,8 +652,15 @@ def bitfield_extract_from_sext_inreg : GICombineRule<
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[{ return Helper.matchBitfieldExtractFromSExtInReg(*${root}, ${info}); }]),
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(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
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def bitfield_extract_from_shr : GICombineRule<
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(defs root:$root, build_fn_matchinfo:$info),
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(match (wip_match_opcode G_ASHR, G_LSHR):$root,
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[{ return Helper.matchBitfieldExtractFromShr(*${root}, ${info}); }]),
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(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
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def form_bitfield_extract : GICombineGroup<[bitfield_extract_from_sext_inreg,
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bitfield_extract_from_and]>;
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bitfield_extract_from_and,
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bitfield_extract_from_shr]>;
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def reassoc_ptradd : GICombineRule<
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(defs root:$root, build_fn_matchinfo:$matchinfo),
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(match (wip_match_opcode G_PTR_ADD):$root,
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@ -4128,6 +4128,55 @@ bool CombinerHelper::matchBitfieldExtractFromAnd(
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return true;
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}
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bool CombinerHelper::matchBitfieldExtractFromShr(
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MachineInstr &MI, std::function<void(MachineIRBuilder &)> &MatchInfo) {
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const unsigned Opcode = MI.getOpcode();
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assert(Opcode == TargetOpcode::G_ASHR || Opcode == TargetOpcode::G_LSHR);
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const Register Dst = MI.getOperand(0).getReg();
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const unsigned ExtrOpcode = Opcode == TargetOpcode::G_ASHR
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? TargetOpcode::G_SBFX
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: TargetOpcode::G_UBFX;
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// Check if the type we would use for the extract is legal
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LLT Ty = MRI.getType(Dst);
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LLT ExtractTy = getTargetLowering().getPreferredShiftAmountTy(Ty);
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if (!LI || !LI->isLegalOrCustom({ExtrOpcode, {Ty, ExtractTy}}))
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return false;
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Register ShlSrc;
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int64_t ShrAmt;
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int64_t ShlAmt;
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const unsigned Size = Ty.getScalarSizeInBits();
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// Try to match shr (shl x, c1), c2
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if (!mi_match(Dst, MRI,
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m_BinOp(Opcode,
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m_OneNonDBGUse(m_GShl(m_Reg(ShlSrc), m_ICst(ShlAmt))),
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m_ICst(ShrAmt))))
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return false;
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// Make sure that the shift sizes can fit a bitfield extract
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if (ShlAmt < 0 || ShlAmt > ShrAmt || ShrAmt >= Size)
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return false;
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// Skip this combine if the G_SEXT_INREG combine could handle it
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if (Opcode == TargetOpcode::G_ASHR && ShlAmt == ShrAmt)
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return false;
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// Calculate start position and width of the extract
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const int64_t Pos = ShrAmt - ShlAmt;
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const int64_t Width = Size - ShrAmt;
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MatchInfo = [=](MachineIRBuilder &B) {
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auto WidthCst = B.buildConstant(ExtractTy, Width);
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auto PosCst = B.buildConstant(ExtractTy, Pos);
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B.buildInstr(ExtrOpcode, {Dst}, {ShlSrc, PosCst, WidthCst});
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};
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return true;
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}
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bool CombinerHelper::reassociationCanBreakAddressingModePattern(
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MachineInstr &PtrAdd) {
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assert(PtrAdd.getOpcode() == TargetOpcode::G_PTR_ADD);
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@ -0,0 +1,178 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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# Check that we can fold a G_ASHR/G_LSHR fed by a G_SHL into a G_SBFX/G_UBFX.
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---
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name: apply_ashr_shl_to_sbfx
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legalized: true
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: apply_ashr_shl_to_sbfx
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
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; CHECK: [[SBFX:%[0-9]+]]:_(s32) = G_SBFX [[COPY]], [[C1]](s32), [[C]]
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; CHECK: $w0 = COPY [[SBFX]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 5
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%2:_(s32) = G_CONSTANT i32 16
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%3:_(s32) = G_SHL %0, %1
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%4:_(s32) = G_ASHR %3, %2
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$w0 = COPY %4(s32)
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...
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---
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name: apply_ashr_shl_to_sbfx_lower_bound
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legalized: true
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: apply_ashr_shl_to_sbfx_lower_bound
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: [[SBFX:%[0-9]+]]:_(s32) = G_SBFX [[COPY]], [[C]](s32), [[C]]
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; CHECK: $w0 = COPY [[SBFX]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 30
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%2:_(s32) = G_CONSTANT i32 31
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%3:_(s32) = G_SHL %0, %1
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%4:_(s32) = G_ASHR %3, %2
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$w0 = COPY %4(s32)
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...
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---
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name: apply_ashr_shl_to_sbfx_upper_bound
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legalized: true
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: apply_ashr_shl_to_sbfx_upper_bound
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
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; CHECK: [[SBFX:%[0-9]+]]:_(s32) = G_SBFX [[COPY]], [[C1]](s32), [[C]]
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; CHECK: $w0 = COPY [[SBFX]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 1
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%2:_(s32) = G_CONSTANT i32 31
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%3:_(s32) = G_SHL %0, %1
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%4:_(s32) = G_ASHR %3, %2
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$w0 = COPY %4(s32)
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...
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---
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name: apply_lshr_shl_to_ubfx
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legalized: true
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: apply_lshr_shl_to_ubfx
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
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; CHECK: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[C1]](s32), [[C]]
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; CHECK: $w0 = COPY [[UBFX]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 5
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%2:_(s32) = G_CONSTANT i32 16
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%3:_(s32) = G_SHL %0, %1
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%4:_(s32) = G_LSHR %3, %2
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$w0 = COPY %4(s32)
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...
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---
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name: apply_lshr_shl_to_ubfx_lower_bound
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legalized: true
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: apply_lshr_shl_to_ubfx_lower_bound
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[C]](s32), [[C]]
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; CHECK: $w0 = COPY [[UBFX]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 30
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%2:_(s32) = G_CONSTANT i32 31
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%3:_(s32) = G_SHL %0, %1
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%4:_(s32) = G_LSHR %3, %2
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$w0 = COPY %4(s32)
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...
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---
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name: apply_lshr_shl_to_ubfx_upper_bound
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legalized: true
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: apply_lshr_shl_to_ubfx_upper_bound
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
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; CHECK: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[C1]](s32), [[C]]
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; CHECK: $w0 = COPY [[UBFX]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 1
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%2:_(s32) = G_CONSTANT i32 31
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%3:_(s32) = G_SHL %0, %1
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%4:_(s32) = G_LSHR %3, %2
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$w0 = COPY %4(s32)
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...
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---
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name: dont_apply_pos_out_of_bounds
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legalized: true
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: dont_apply_pos_out_of_bounds
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
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; CHECK: $w0 = COPY [[ASHR]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 5
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%2:_(s32) = G_CONSTANT i32 2
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%3:_(s32) = G_SHL %0, %1
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%4:_(s32) = G_ASHR %3, %2
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$w0 = COPY %4(s32)
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...
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---
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name: dont_apply_no_constant
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legalized: true
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: dont_apply_no_constant
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
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; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
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; CHECK: $w0 = COPY [[ASHR]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32) = G_CONSTANT i32 2
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%3:_(s32) = G_SHL %0, %1
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%4:_(s32) = G_ASHR %3, %2
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$w0 = COPY %4(s32)
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...
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---
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name: dont_apply_more_than_one_use
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legalized: true
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: dont_apply_more_than_one_use
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
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; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SHL]], [[ASHR]]
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; CHECK: $w0 = COPY [[MUL]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_CONSTANT i32 5
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%2:_(s32) = G_CONSTANT i32 16
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%3:_(s32) = G_SHL %0, %1
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%4:_(s32) = G_ASHR %3, %2
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%5:_(s32) = G_MUL %3, %4
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$w0 = COPY %5(s32)
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...
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@ -156,8 +156,7 @@ define i64 @test_rev_x_srl32_shift(i64 %a) {
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;
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; GISEL-LABEL: test_rev_x_srl32_shift:
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; GISEL: // %bb.0: // %entry
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; GISEL-NEXT: lsl x8, x0, #33
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; GISEL-NEXT: lsr x8, x8, #35
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; GISEL-NEXT: ubfx x8, x0, #2, #29
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; GISEL-NEXT: rev x8, x8
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; GISEL-NEXT: lsr x0, x8, #32
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; GISEL-NEXT: ret
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@ -399,8 +399,7 @@ define amdgpu_kernel void @bfe_u32_test_4(i32 addrspace(1)* %out, i32 addrspace(
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_lshl_b32 s0, s0, 31
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; GFX6-NEXT: s_lshr_b32 s0, s0, 31
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; GFX6-NEXT: s_bfe_u32 s0, s0, 0x10000
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; GFX6-NEXT: s_bfe_u32 s0, s0, 0x1001f
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; GFX6-NEXT: v_mov_b32_e32 v0, s0
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; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
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@ -1059,8 +1058,7 @@ define amdgpu_kernel void @shl_lshr(i32 addrspace(1)* %out, i32 %a) #0 {
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; GFX6-NEXT: s_mov_b32 s6, -1
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_lshl_b32 s0, s0, 9
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; GFX6-NEXT: s_lshr_b32 s0, s0, 11
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; GFX6-NEXT: s_bfe_u32 s0, s0, 0x150002
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; GFX6-NEXT: v_mov_b32_e32 v0, s0
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; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GFX6-NEXT: s_endpgm
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