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[AArch64] Add additional vecreduce fmax/fmin legalization tests (NFC) 

Add a vector widening test with ninf flag to the existing fmax
tests, and mirror them over into fmin tests.
This commit is contained in:
Nikita Popov 2020-09-14 21:11:56 +02:00
parent f06090243d
commit cc94720728
2 changed files with 101 additions and 0 deletions
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12
llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
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@ -56,6 +56,18 @@ define float @test_v3f32(<3 x float> %a) nounwind {
ret float %b
}
define float @test_v3f32_ninf(<3 x float> %a) nounwind {
; CHECK-LABEL: test_v3f32_ninf:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #2143289344
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: mov v0.s[3], v1.s[0]
; CHECK-NEXT: fmaxnmv s0, v0.4s
; CHECK-NEXT: ret
%b = call nnan ninf float @llvm.experimental.vector.reduce.fmax.v3f32(<3 x float> %a)
ret float %b
}
define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
; CHECK-LABEL: test_v2f128:
; CHECK: // %bb.0:

89
llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll Normal file
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@ -0,0 +1,89 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
declare half @llvm.experimental.vector.reduce.fmin.v1f16(<1 x half> %a)
declare float @llvm.experimental.vector.reduce.fmin.v1f32(<1 x float> %a)
declare double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> %a)
declare fp128 @llvm.experimental.vector.reduce.fmin.v1f128(<1 x fp128> %a)
declare float @llvm.experimental.vector.reduce.fmin.v3f32(<3 x float> %a)
declare fp128 @llvm.experimental.vector.reduce.fmin.v2f128(<2 x fp128> %a)
declare float @llvm.experimental.vector.reduce.fmin.v16f32(<16 x float> %a)
define half @test_v1f16(<1 x half> %a) nounwind {
; CHECK-LABEL: test_v1f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ret
%b = call nnan half @llvm.experimental.vector.reduce.fmin.v1f16(<1 x half> %a)
ret half %b
}
define float @test_v1f32(<1 x float> %a) nounwind {
; CHECK-LABEL: test_v1f32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: ret
%b = call nnan float @llvm.experimental.vector.reduce.fmin.v1f32(<1 x float> %a)
ret float %b
}
define double @test_v1f64(<1 x double> %a) nounwind {
; CHECK-LABEL: test_v1f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ret
%b = call nnan double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> %a)
ret double %b
}
define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
; CHECK-LABEL: test_v1f128:
; CHECK: // %bb.0:
; CHECK-NEXT: ret
%b = call nnan fp128 @llvm.experimental.vector.reduce.fmin.v1f128(<1 x fp128> %a)
ret fp128 %b
}
define float @test_v3f32(<3 x float> %a) nounwind {
; CHECK-LABEL: test_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #2143289344
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: mov v0.s[3], v1.s[0]
; CHECK-NEXT: fminnmv s0, v0.4s
; CHECK-NEXT: ret
%b = call nnan float @llvm.experimental.vector.reduce.fmin.v3f32(<3 x float> %a)
ret float %b
}
define float @test_v3f32_ninf(<3 x float> %a) nounwind {
; CHECK-LABEL: test_v3f32_ninf:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #2143289344
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: mov v0.s[3], v1.s[0]
; CHECK-NEXT: fminnmv s0, v0.4s
; CHECK-NEXT: ret
%b = call nnan ninf float @llvm.experimental.vector.reduce.fmin.v3f32(<3 x float> %a)
ret float %b
}
define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
; CHECK-LABEL: test_v2f128:
; CHECK: // %bb.0:
; CHECK-NEXT: b fminl
%b = call nnan fp128 @llvm.experimental.vector.reduce.fmin.v2f128(<2 x fp128> %a)
ret fp128 %b
}
define float @test_v16f32(<16 x float> %a) nounwind {
; CHECK-LABEL: test_v16f32:
; CHECK: // %bb.0:
; CHECK-NEXT: fminnm v1.4s, v1.4s, v3.4s
; CHECK-NEXT: fminnm v0.4s, v0.4s, v2.4s
; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
; CHECK-NEXT: fminnmv s0, v0.4s
; CHECK-NEXT: ret
%b = call nnan float @llvm.experimental.vector.reduce.fmin.v16f32(<16 x float> %a)
ret float %b
}