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Added the LODS (load byte into register, usually 

as part string parsing) instructions to the Intel
instruction tables.

llvm-svn: 82089
This commit is contained in:
Sean Callanan 2009-09-16 22:59:28 +00:00
parent 11083da4d0
commit cc774e7476
2 changed files with 10 additions and 0 deletions
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4
llvm/lib/Target/X86/X86Instr64bit.td
View File

@ -1549,6 +1549,10 @@ def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
"lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
// String manipulation instructions
def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//

6
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -3685,6 +3685,12 @@ def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
"lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
// String manipulation instructions
def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
def LODSD : I<0xAD, RawFrm, (outs), (ins), "lodsd", []>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//