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AMDGPU: Add failing testcase for live interval construction 

llvm-svn: 248067
This commit is contained in:
Matt Arsenault 2015-09-19 00:03:56 +00:00
parent 40b180e7ee
commit cc5d106263
1 changed files with 29 additions and 0 deletions
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29
llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll Normal file
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; XFAIL: *
; RUN: llc -march=amdgcn -verify-machineinstrs -verify-coalescing < %s
; The original and requires materializing a 64-bit immediate for
; s_and_b64. This is split into 2 x v_and_i32, part of the immediate
; is folded through the reg_sequence into the v_and_i32 operand, and
; only half of the result is ever used.
;
; During live interval construction, the first sub register def is
; incorrectly marked as dead.
declare i32 @llvm.r600.read.tidig.x() #1
define void @dead_def_subregister(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) #0 {
%tid = call i32 @llvm.r600.read.tidig.x() #1
%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
%val = load i64, i64 addrspace(1)* %in.gep
%lshr = shl i64 %val, 24
%and1 = and i64 %lshr, 2190433320969 ; (255 << 33) | 9
%vec = bitcast i64 %and1 to <2 x i32>
%elt1 = extractelement <2 x i32> %vec, i32 1
store i32 %elt1, i32 addrspace(1)* %out
ret void
}
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }