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Expand Op0Mask by one bit in preparation for the PadLock prefixes. 

Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.

llvm-svn: 128822
This commit is contained in:
Joerg Sonnenberger 2011-04-04 15:58:30 +00:00
parent 8933907b51
commit cc53d9919f
3 changed files with 51 additions and 50 deletions
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60
llvm/lib/Target/X86/X86InstrFormats.td
View File

@ -91,21 +91,21 @@ class REX_W { bit hasREX_WPrefix = 1; }
class LOCK { bit hasLockPrefix = 1; } class LOCK { bit hasLockPrefix = 1; }
class SegFS { bits<2> SegOvrBits = 1; } class SegFS { bits<2> SegOvrBits = 1; }
class SegGS { bits<2> SegOvrBits = 2; } class SegGS { bits<2> SegOvrBits = 2; }
class TB { bits<4> Prefix = 1; } class TB { bits<5> Prefix = 1; }
class REP { bits<4> Prefix = 2; } class REP { bits<5> Prefix = 2; }
class D8 { bits<4> Prefix = 3; } class D8 { bits<5> Prefix = 3; }
class D9 { bits<4> Prefix = 4; } class D9 { bits<5> Prefix = 4; }
class DA { bits<4> Prefix = 5; } class DA { bits<5> Prefix = 5; }
class DB { bits<4> Prefix = 6; } class DB { bits<5> Prefix = 6; }
class DC { bits<4> Prefix = 7; } class DC { bits<5> Prefix = 7; }
class DD { bits<4> Prefix = 8; } class DD { bits<5> Prefix = 8; }
class DE { bits<4> Prefix = 9; } class DE { bits<5> Prefix = 9; }
class DF { bits<4> Prefix = 10; } class DF { bits<5> Prefix = 10; }
class XD { bits<4> Prefix = 11; } class XD { bits<5> Prefix = 11; }
class XS { bits<4> Prefix = 12; } class XS { bits<5> Prefix = 12; }
class T8 { bits<4> Prefix = 13; } class T8 { bits<5> Prefix = 13; }
class TA { bits<4> Prefix = 14; } class TA { bits<5> Prefix = 14; }
class TF { bits<4> Prefix = 15; } class TF { bits<5> Prefix = 15; }
class VEX { bit hasVEXPrefix = 1; } class VEX { bit hasVEXPrefix = 1; }
class VEX_W { bit hasVEX_WPrefix = 1; } class VEX_W { bit hasVEX_WPrefix = 1; }
class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; } class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
@ -136,7 +136,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix? bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
bits<4> Prefix = 0; // Which prefix byte does this inst have? bits<5> Prefix = 0; // Which prefix byte does this inst have?
bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix? bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
FPFormat FPForm = NotFP; // What flavor of FP instruction is this? FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
@ -154,20 +154,20 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
let TSFlags{5-0} = FormBits; let TSFlags{5-0} = FormBits;
let TSFlags{6} = hasOpSizePrefix; let TSFlags{6} = hasOpSizePrefix;
let TSFlags{7} = hasAdSizePrefix; let TSFlags{7} = hasAdSizePrefix;
let TSFlags{11-8} = Prefix; let TSFlags{12-8} = Prefix;
let TSFlags{12} = hasREX_WPrefix; let TSFlags{13} = hasREX_WPrefix;
let TSFlags{15-13} = ImmT.Value; let TSFlags{16-14} = ImmT.Value;
let TSFlags{18-16} = FPForm.Value; let TSFlags{19-17} = FPForm.Value;
let TSFlags{19} = hasLockPrefix; let TSFlags{20} = hasLockPrefix;
let TSFlags{21-20} = SegOvrBits; let TSFlags{22-21} = SegOvrBits;
let TSFlags{23-22} = ExeDomain.Value; let TSFlags{24-23} = ExeDomain.Value;
let TSFlags{31-24} = Opcode; let TSFlags{32-25} = Opcode;
let TSFlags{32} = hasVEXPrefix; let TSFlags{33} = hasVEXPrefix;
let TSFlags{33} = hasVEX_WPrefix; let TSFlags{34} = hasVEX_WPrefix;
let TSFlags{34} = hasVEX_4VPrefix; let TSFlags{35} = hasVEX_4VPrefix;
let TSFlags{35} = hasVEX_i8ImmReg; let TSFlags{36} = hasVEX_i8ImmReg;
let TSFlags{36} = hasVEX_L; let TSFlags{37} = hasVEX_L;
let TSFlags{37} = has3DNow0F0FOpcode; let TSFlags{38} = has3DNow0F0FOpcode;
} }
class PseudoI<dag oops, dag iops, list<dag> pattern> class PseudoI<dag oops, dag iops, list<dag> pattern>

23
llvm/lib/Target/X86/X86InstrInfo.h
View File

@ -347,7 +347,7 @@ namespace X86II {
// set, there is no prefix byte for obtaining a multibyte opcode. // set, there is no prefix byte for obtaining a multibyte opcode.
// //
Op0Shift = 8, Op0Shift = 8,
Op0Mask = 0xF << Op0Shift, Op0Mask = 0x1F << Op0Shift,
// TB - TwoByte - Set if this instruction has a two byte opcode, which // TB - TwoByte - Set if this instruction has a two byte opcode, which
// starts with a 0x0F byte before the real opcode. // starts with a 0x0F byte before the real opcode.
@ -380,13 +380,13 @@ namespace X86II {
// etc. We only cares about REX.W and REX.R bits and only the former is // etc. We only cares about REX.W and REX.R bits and only the former is
// statically determined. // statically determined.
// //
REXShift = 12, REXShift = Op0Shift + 5,
REX_W = 1 << REXShift, REX_W = 1 << REXShift,
//===------------------------------------------------------------------===// //===------------------------------------------------------------------===//
// This three-bit field describes the size of an immediate operand. Zero is // This three-bit field describes the size of an immediate operand. Zero is
// unused so that we can tell if we forgot to set a value. // unused so that we can tell if we forgot to set a value.
ImmShift = 13, ImmShift = REXShift + 1,
ImmMask = 7 << ImmShift, ImmMask = 7 << ImmShift,
Imm8 = 1 << ImmShift, Imm8 = 1 << ImmShift,
Imm8PCRel = 2 << ImmShift, Imm8PCRel = 2 << ImmShift,
@ -400,7 +400,7 @@ namespace X86II {
// FP Instruction Classification... Zero is non-fp instruction. // FP Instruction Classification... Zero is non-fp instruction.
// FPTypeMask - Mask for all of the FP types... // FPTypeMask - Mask for all of the FP types...
FPTypeShift = 16, FPTypeShift = ImmShift + 3,
FPTypeMask = 7 << FPTypeShift, FPTypeMask = 7 << FPTypeShift,
// NotFP - The default, set for instructions that do not use FP registers. // NotFP - The default, set for instructions that do not use FP registers.
@ -433,25 +433,26 @@ namespace X86II {
SpecialFP = 7 << FPTypeShift, SpecialFP = 7 << FPTypeShift,
// Lock prefix // Lock prefix
LOCKShift = 19, LOCKShift = FPTypeShift + 3,
LOCK = 1 << LOCKShift, LOCK = 1 << LOCKShift,
// Segment override prefixes. Currently we just need ability to address // Segment override prefixes. Currently we just need ability to address
// stuff in gs and fs segments. // stuff in gs and fs segments.
SegOvrShift = 20, SegOvrShift = LOCKShift + 1,
SegOvrMask = 3 << SegOvrShift, SegOvrMask = 3 << SegOvrShift,
FS = 1 << SegOvrShift, FS = 1 << SegOvrShift,
GS = 2 << SegOvrShift, GS = 2 << SegOvrShift,
// Execution domain for SSE instructions in bits 22, 23. // Execution domain for SSE instructions in bits 23, 24.
// 0 in bits 22-23 means normal, non-SSE instruction. // 0 in bits 23-24 means normal, non-SSE instruction.
SSEDomainShift = 22, SSEDomainShift = SegOvrShift + 2,
OpcodeShift = 24, OpcodeShift = SSEDomainShift + 2,
OpcodeMask = 0xFF << OpcodeShift, OpcodeMask = 0xFF << OpcodeShift,
//===------------------------------------------------------------------===// //===------------------------------------------------------------------===//
/// VEX - The opcode prefix used by AVX instructions /// VEX - The opcode prefix used by AVX instructions
VEXShift = OpcodeShift + 8,
VEX = 1U << 0, VEX = 1U << 0,
/// VEX_W - Has a opcode specific functionality, but is used in the same /// VEX_W - Has a opcode specific functionality, but is used in the same
@ -549,7 +550,7 @@ namespace X86II {
case X86II::MRMDestMem: case X86II::MRMDestMem:
return 0; return 0;
case X86II::MRMSrcMem: { case X86II::MRMSrcMem: {
bool HasVEX_4V = (TSFlags >> 32) & X86II::VEX_4V; bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
unsigned FirstMemOp = 1; unsigned FirstMemOp = 1;
if (HasVEX_4V) if (HasVEX_4V)
++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).

18
llvm/lib/Target/X86/X86MCCodeEmitter.cpp
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@ -382,7 +382,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
const TargetInstrDesc &Desc, const TargetInstrDesc &Desc,
raw_ostream &OS) const { raw_ostream &OS) const {
bool HasVEX_4V = false; bool HasVEX_4V = false;
if ((TSFlags >> 32) & X86II::VEX_4V) if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
HasVEX_4V = true; HasVEX_4V = true;
// VEX_R: opcode externsion equivalent to REX.R in // VEX_R: opcode externsion equivalent to REX.R in
@ -446,10 +446,10 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
if (TSFlags & X86II::OpSize) if (TSFlags & X86II::OpSize)
VEX_PP = 0x01; VEX_PP = 0x01;
if ((TSFlags >> 32) & X86II::VEX_W) if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
VEX_W = 1; VEX_W = 1;
if ((TSFlags >> 32) & X86II::VEX_L) if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
VEX_L = 1; VEX_L = 1;
switch (TSFlags & X86II::Op0Mask) { switch (TSFlags & X86II::Op0Mask) {
@ -518,7 +518,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
// If the last register should be encoded in the immediate field // If the last register should be encoded in the immediate field
// do not use any bit from VEX prefix to this register, ignore it // do not use any bit from VEX prefix to this register, ignore it
if ((TSFlags >> 32) & X86II::VEX_I8IMM) if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM)
NumOps--; NumOps--;
for (; CurOp != NumOps; ++CurOp) { for (; CurOp != NumOps; ++CurOp) {
@ -819,9 +819,9 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
// It uses the VEX.VVVV field? // It uses the VEX.VVVV field?
bool HasVEX_4V = false; bool HasVEX_4V = false;
if ((TSFlags >> 32) & X86II::VEX) if ((TSFlags >> X86II::VEXShift) & X86II::VEX)
HasVEXPrefix = true; HasVEXPrefix = true;
if ((TSFlags >> 32) & X86II::VEX_4V) if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
HasVEX_4V = true; HasVEX_4V = true;
@ -837,7 +837,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
if ((TSFlags >> 32) & X86II::Has3DNow0F0FOpcode) if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
BaseOpcode = 0x0F; // Weird 3DNow! encoding. BaseOpcode = 0x0F; // Weird 3DNow! encoding.
unsigned SrcRegNum = 0; unsigned SrcRegNum = 0;
@ -994,7 +994,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
if (CurOp != NumOps) { if (CurOp != NumOps) {
// The last source register of a 4 operand instruction in AVX is encoded // The last source register of a 4 operand instruction in AVX is encoded
// in bits[7:4] of a immediate byte, and bits[3:0] are ignored. // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
if ((TSFlags >> 32) & X86II::VEX_I8IMM) { if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
const MCOperand &MO = MI.getOperand(CurOp++); const MCOperand &MO = MI.getOperand(CurOp++);
bool IsExtReg = bool IsExtReg =
X86InstrInfo::isX86_64ExtendedReg(MO.getReg()); X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
@ -1017,7 +1017,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
} }
} }
if ((TSFlags >> 32) & X86II::Has3DNow0F0FOpcode) if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);