forked from OSchip/llvm-project
[AMDGPU] Rename $dst operand to $vdst for VOP instructions.
Summary: This change renames output operand for VOP instructions from dst to vdst. This is needed to enable decoding named operands for disassembler. Reviewers: vpykhtin, tstellarAMD, arsenm Subscribers: arsenm, llvm-commits, nhaustov Projects: #llvm-amdgpu-spb Differential Revision: http://reviews.llvm.org/D16920 llvm-svn: 260986
This commit is contained in:
Tom Stellard
parent
845435c86a
commit
cc4c8718ed
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@ -362,8 +362,7 @@ class VOP2_MADKe <bits<6> op> : Enc64 {
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let Inst{63-32} = src2;
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}
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class VOP3e <bits<9> op> : Enc64 {
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bits<8> vdst;
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class VOP3a <bits<9> op> : Enc64 {
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bits<2> src0_modifiers;
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bits<9> src0;
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bits<2> src1_modifiers;
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@ -373,7 +372,6 @@ class VOP3e <bits<9> op> : Enc64 {
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bits<1> clamp;
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bits<2> omod;
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let Inst{7-0} = vdst;
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let Inst{8} = src0_modifiers{1};
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let Inst{9} = src1_modifiers{1};
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let Inst{10} = src2_modifiers{1};
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@ -389,6 +387,20 @@ class VOP3e <bits<9> op> : Enc64 {
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let Inst{63} = src2_modifiers{0};
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}
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class VOP3e <bits<9> op> : VOP3a <op> {
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bits<8> vdst;
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let Inst{7-0} = vdst;
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}
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// Encoding used for VOPC instructions encoded as VOP3
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// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
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class VOP3ce <bits<9> op> : VOP3a <op> {
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bits<8> sdst;
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let Inst{7-0} = sdst;
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}
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class VOP3be <bits<9> op> : Enc64 {
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bits<8> vdst;
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bits<2> src0_modifiers;
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@ -1244,7 +1244,7 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
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}
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}
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const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
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const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::vdst);
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const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
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const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
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const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
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@ -1186,8 +1186,8 @@ class getInsDPP <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs,
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// Returns the assembly string for the inputs and outputs of a VOP[12C]
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// instruction. This does not add the _e32 suffix, so it can be reused
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// by getAsm64.
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class getAsm32 <bit HasDst, int NumSrcArgs> {
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string dst = "$dst";
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class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
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string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
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string src0 = ", $src0";
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string src1 = ", $src1";
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string src2 = ", $src2";
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@ -1199,7 +1199,8 @@ class getAsm32 <bit HasDst, int NumSrcArgs> {
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// Returns the assembly string for the inputs and outputs of a VOP3
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// instruction.
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class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers> {
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class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
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string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
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string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
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string src1 = !if(!eq(NumSrcArgs, 1), "",
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!if(!eq(NumSrcArgs, 2), " $src1_modifiers",
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@ -1207,19 +1208,20 @@ class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers> {
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string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
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string ret =
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!if(!eq(HasModifiers, 0),
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getAsm32<HasDst, NumSrcArgs>.ret,
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"$dst, "#src0#src1#src2#"$clamp"#"$omod");
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getAsm32<HasDst, NumSrcArgs, DstVT>.ret,
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dst#", "#src0#src1#src2#"$clamp"#"$omod");
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}
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class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers> {
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class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
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string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
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string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
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string src1 = !if(!eq(NumSrcArgs, 1), "",
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!if(!eq(NumSrcArgs, 2), " $src1_modifiers",
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" $src1_modifiers,"));
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string args = !if(!eq(HasModifiers, 0),
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getAsm32<0, NumSrcArgs>.ret,
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getAsm32<0, NumSrcArgs, DstVT>.ret,
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src0#src1);
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string ret = " $dst"#args#", $dpp_ctrl, "#"$bound_ctrl, "#"$bank_mask, "#"$row_mask";
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string ret = " "#dst#args#", $dpp_ctrl, "#"$bound_ctrl, "#"$bank_mask, "#"$row_mask";
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}
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class VOPProfile <list<ValueType> _ArgVT> {
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@ -1245,22 +1247,23 @@ class VOPProfile <list<ValueType> _ArgVT> {
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field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
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field bit HasModifiers = hasModifiers<Src0VT>.ret;
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field dag Outs = !if(HasDst,(outs DstRC:$dst),(outs));
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field dag Outs = !if(HasDst,(outs DstRC:$vdst),(outs));
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// VOP3b instructions are a special case with a second explicit
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// output. This is manually overridden for them.
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field dag Outs32 = Outs;
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field dag Outs64 = Outs;
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field dag OutsDPP = (outs DstRCDPP:$dst);
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field dag OutsDPP = !if(!eq(DstVT.Size, 1), (outs DstRCDPP:$sdst), // sdst for VOPC
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(outs DstRCDPP:$vdst));
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field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
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field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
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HasModifiers>.ret;
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field dag InsDPP = getInsDPP<Src0DPP, Src1DPP, NumSrcArgs, HasModifiers>.ret;
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field string Asm32 = getAsm32<HasDst, NumSrcArgs>.ret;
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field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers>.ret;
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field string AsmDPP = getAsmDPP<HasDst, NumSrcArgs, HasModifiers>.ret;
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field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
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field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
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field string AsmDPP = getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
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}
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// FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
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@ -1295,10 +1298,10 @@ def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
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// Write out to vcc or arbitrary SGPR.
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def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> {
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let Asm32 = "$dst, vcc, $src0, $src1";
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let Asm64 = "$dst, $sdst, $src0, $src1";
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let Outs32 = (outs DstRC:$dst);
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let Outs64 = (outs DstRC:$dst, SReg_64:$sdst);
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let Asm32 = "$vdst, vcc, $src0, $src1";
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let Asm64 = "$vdst, $sdst, $src0, $src1";
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let Outs32 = (outs DstRC:$vdst);
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let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
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}
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// Write out to vcc or arbitrary SGPR and read in from vcc or
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@ -1310,10 +1313,10 @@ def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
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// restriction. SGPRs are still allowed because it should
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// technically be possible to use VCC again as src0.
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let Src0RC32 = VCSrc_32;
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let Asm32 = "$dst, vcc, $src0, $src1, vcc";
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let Asm64 = "$dst, $sdst, $src0, $src1, $src2";
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let Outs32 = (outs DstRC:$dst);
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let Outs64 = (outs DstRC:$dst, SReg_64:$sdst);
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let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
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let Asm64 = "$vdst, $sdst, $src0, $src1, $src2";
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let Outs32 = (outs DstRC:$vdst);
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let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
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// Suppress src2 implied by type since the 32-bit encoding uses an
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// implicit VCC use.
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@ -1342,11 +1345,12 @@ class VOPC_Profile<ValueType vt0, ValueType vt1 = vt0> : VOPProfile <[i1, vt0, v
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let Asm32 = "vcc, $src0, $src1";
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// The destination for 32-bit encoding is implicit.
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let HasDst32 = 0;
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let Outs64 = (outs DstRC:$sdst);
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}
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class VOPC_Class_Profile<ValueType vt> : VOPC_Profile<vt, i32> {
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let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
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let Asm64 = "$dst, $src0_modifiers, $src1";
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let Asm64 = "$sdst, $src0_modifiers, $src1";
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}
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def VOPC_I1_F32_F32 : VOPC_Profile<f32>;
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@ -1363,25 +1367,26 @@ def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
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def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
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let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
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let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
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let Asm64 = "$dst, $src0, $src1, $src2";
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let Asm64 = "$vdst, $src0, $src1, $src2";
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}
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def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
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def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
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field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
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field string Asm = "$dst, $src0, $vsrc1, $src2";
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field string Asm = "$vdst, $src0, $vsrc1, $src2";
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}
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def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> {
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let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
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let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
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HasModifiers>.ret;
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let Asm32 = getAsm32<1, 2>.ret;
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let Asm64 = getAsm64<1, 2, HasModifiers>.ret;
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let Asm32 = getAsm32<1, 2, f32>.ret;
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let Asm64 = getAsm64<1, 2, HasModifiers, f32>.ret;
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}
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def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
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def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
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def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
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// This class is used only with VOPC instructions. Use $sdst for out operand
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class SIInstAlias <string asm, Instruction inst, VOPProfile p> :
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InstAlias <asm, (inst)>, PredicateControl {
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@ -1392,13 +1397,13 @@ class SIInstAlias <string asm, Instruction inst, VOPProfile p> :
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!if (p.HasDst32,
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!if (!eq(p.NumSrcArgs, 0),
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// 1 dst, 0 src
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(inst p.DstRC:$dst),
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(inst p.DstRC:$sdst),
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!if (!eq(p.NumSrcArgs, 1),
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// 1 dst, 1 src
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(inst p.DstRC:$dst, p.Src0RC32:$src0),
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(inst p.DstRC:$sdst, p.Src0RC32:$src0),
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!if (!eq(p.NumSrcArgs, 2),
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// 1 dst, 2 src
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(inst p.DstRC:$dst, p.Src0RC32:$src0, p.Src1RC32:$src1),
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(inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
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// else - unreachable
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(inst)))),
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// else
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@ -1481,8 +1486,6 @@ multiclass VOP1_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
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class VOP1_DPP <vop1 op, string opName, VOPProfile p> :
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VOP1_DPPe <op.VI>,
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VOP_DPP <p.OutsDPP, p.InsDPP, opName#p.AsmDPP, []> {
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// FIXME: remove when we are using the correct names for the encoding fields.
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field bit vdst = 0;
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let AssemblerPredicates = [isVI];
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let src0_modifiers = !if(p.HasModifiers, ?, 0);
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let src1_modifiers = 0;
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@ -1589,6 +1592,22 @@ class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,
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let AssemblerPredicates = [isVI];
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}
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class VOP3_C_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName,
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bit HasMods = 0, bit VOP3Only = 0> :
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VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
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VOP3ce <op>,
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SIMCInstr<opName#"_e64", SISubtarget.SI> {
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let AssemblerPredicates = [isSICI];
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}
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class VOP3_C_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,
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bit HasMods = 0, bit VOP3Only = 0> :
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VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
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VOP3ce_vi <op>,
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SIMCInstr <opName#"_e64", SISubtarget.VI> {
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let AssemblerPredicates = [isVI];
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}
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class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName,
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bit HasMods = 0, bit VOP3Only = 0> :
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VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
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@ -1694,13 +1713,13 @@ multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
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let SchedRW = sched;
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}
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def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods>,
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def _si : VOP3_C_Real_si <op.SI3, outs, ins, asm, opName, HasMods>,
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VOP3DisableFields<1, 0, HasMods> {
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let Defs = !if(defExec, [EXEC], []);
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let SchedRW = sched;
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}
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def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName, HasMods>,
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def _vi : VOP3_C_Real_vi <op.VI3, outs, ins, asm, opName, HasMods>,
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VOP3DisableFields<1, 0, HasMods> {
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let Defs = !if(defExec, [EXEC], []);
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let SchedRW = sched;
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@ -1743,9 +1762,9 @@ multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
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SDPatternOperator node = null_frag> : VOP1_Helper <
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op, opName, P, [],
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!if(P.HasModifiers,
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[(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
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[(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
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i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0))])
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[(set P.DstVT:$vdst, (node P.Src0VT:$src0))])
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>;
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multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
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@ -1755,9 +1774,9 @@ multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
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defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
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!if(P.HasModifiers,
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[(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
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[(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
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i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
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[(set P.DstVT:$vdst, (node P.Src0VT:$src0))]),
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opName, P.HasModifiers>;
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}
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@ -1775,11 +1794,11 @@ multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
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string revOp = opName> : VOP2_Helper <
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op, opName, P, [],
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!if(P.HasModifiers,
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[(set P.DstVT:$dst,
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[(set P.DstVT:$vdst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
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[(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
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revOp
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>;
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@ -1791,11 +1810,11 @@ multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
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defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
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!if(P.HasModifiers,
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[(set P.DstVT:$dst,
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[(set P.DstVT:$vdst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
|
||||
[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
|
||||
[(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
|
||||
opName, revOp, P.HasModifiers>;
|
||||
}
|
||||
|
||||
|
|
@ -1818,11 +1837,11 @@ multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
|
|||
string revOp = opName> : VOP2b_Helper <
|
||||
op, opName, P, [],
|
||||
!if(P.HasModifiers,
|
||||
[(set P.DstVT:$dst,
|
||||
[(set P.DstVT:$vdst,
|
||||
(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
|
||||
i1:$clamp, i32:$omod)),
|
||||
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
|
||||
[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
|
||||
[(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
|
||||
revOp, !eq(P.NumSrcArgs, 3)
|
||||
>;
|
||||
|
||||
|
|
@ -1842,11 +1861,11 @@ multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
|
|||
: VOP2_VI3_Helper <
|
||||
op, opName, P, [],
|
||||
!if(P.HasModifiers,
|
||||
[(set P.DstVT:$dst,
|
||||
[(set P.DstVT:$vdst,
|
||||
(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
|
||||
i1:$clamp, i32:$omod)),
|
||||
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
|
||||
[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
|
||||
[(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
|
||||
revOp
|
||||
>;
|
||||
|
||||
|
|
@ -1919,7 +1938,7 @@ multiclass VOPC_Helper <vopc op, string opName, list<dag> pat32,
|
|||
defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched,
|
||||
revOp>;
|
||||
|
||||
defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64,
|
||||
defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$sdst), p.Ins64, opName#p.Asm64, pat64,
|
||||
opName, p.HasModifiers, DefExec, revOp, sched>;
|
||||
}
|
||||
|
||||
|
|
@ -1930,7 +1949,7 @@ multiclass VOPC_Class_Helper <vopc op, string opName, list<dag> pat32,
|
|||
VOPProfile p, list<SchedReadWrite> sched> {
|
||||
defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched>;
|
||||
|
||||
defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64,
|
||||
defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$sdst), p.Ins64, opName#p.Asm64, pat64,
|
||||
opName, p.HasModifiers, DefExec, revOp, sched>,
|
||||
VOP3DisableModFields<1, 0, 0>;
|
||||
}
|
||||
|
|
@ -1943,12 +1962,12 @@ multiclass VOPCInst <vopc op, string opName,
|
|||
VOPC_Helper <
|
||||
op, opName, [],
|
||||
!if(P.HasModifiers,
|
||||
[(set i1:$dst,
|
||||
[(set i1:$sdst,
|
||||
(setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
|
||||
i1:$clamp, i32:$omod)),
|
||||
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
|
||||
cond))],
|
||||
[(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
|
||||
[(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
|
||||
DefExec, revOp, P, sched
|
||||
>;
|
||||
|
||||
|
|
@ -1957,9 +1976,9 @@ multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
|
|||
list<SchedReadWrite> sched> : VOPC_Class_Helper <
|
||||
op, opName, [],
|
||||
!if(P.HasModifiers,
|
||||
[(set i1:$dst,
|
||||
[(set i1:$sdst,
|
||||
(AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
|
||||
[(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
|
||||
[(set i1:$sdst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
|
||||
DefExec, opName, P, sched
|
||||
>;
|
||||
|
||||
|
|
@ -2016,29 +2035,29 @@ multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
|
|||
multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
|
||||
SDPatternOperator node = null_frag, bit VOP3Only = 0> :
|
||||
VOP3_Helper <
|
||||
op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
|
||||
op, opName, (outs P.DstRC.RegClass:$vdst), P.Ins64, P.Asm64,
|
||||
!if(!eq(P.NumSrcArgs, 3),
|
||||
!if(P.HasModifiers,
|
||||
[(set P.DstVT:$dst,
|
||||
[(set P.DstVT:$vdst,
|
||||
(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
|
||||
i1:$clamp, i32:$omod)),
|
||||
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
|
||||
(P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
|
||||
[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
|
||||
[(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1,
|
||||
P.Src2VT:$src2))]),
|
||||
!if(!eq(P.NumSrcArgs, 2),
|
||||
!if(P.HasModifiers,
|
||||
[(set P.DstVT:$dst,
|
||||
[(set P.DstVT:$vdst,
|
||||
(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
|
||||
i1:$clamp, i32:$omod)),
|
||||
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
|
||||
[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
|
||||
[(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
|
||||
/* P.NumSrcArgs == 1 */,
|
||||
!if(P.HasModifiers,
|
||||
[(set P.DstVT:$dst,
|
||||
[(set P.DstVT:$vdst,
|
||||
(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
|
||||
i1:$clamp, i32:$omod))))],
|
||||
[(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
|
||||
[(set P.DstVT:$vdst, (node P.Src0VT:$src0))]))),
|
||||
P.NumSrcArgs, P.HasModifiers, VOP3Only
|
||||
>;
|
||||
|
||||
|
|
@ -2048,14 +2067,14 @@ multiclass VOP3_VCC_Inst <vop3 op, string opName,
|
|||
VOPProfile P,
|
||||
SDPatternOperator node = null_frag> : VOP3_Helper <
|
||||
op, opName,
|
||||
(outs P.DstRC.RegClass:$dst),
|
||||
(outs P.DstRC.RegClass:$vdst),
|
||||
(ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
|
||||
InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
|
||||
InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
|
||||
ClampMod:$clamp,
|
||||
omod:$omod),
|
||||
"$dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
|
||||
[(set P.DstVT:$dst,
|
||||
"$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
|
||||
[(set P.DstVT:$vdst,
|
||||
(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
|
||||
i1:$clamp, i32:$omod)),
|
||||
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
|
||||
|
|
|
|||
|
|
@ -1503,7 +1503,7 @@ defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", VOP_I32_I32_I32>;
|
|||
defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>;
|
||||
defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32", VOP_I32_I32_I32>;
|
||||
|
||||
let Constraints = "$dst = $src2", DisableEncoding="$src2",
|
||||
let Constraints = "$vdst = $src2", DisableEncoding="$src2",
|
||||
isConvertibleToThreeAddress = 1 in {
|
||||
defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_MAC>;
|
||||
}
|
||||
|
|
@ -1850,14 +1850,14 @@ defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64",
|
|||
let isCodeGenOnly = 1, isPseudo = 1 in {
|
||||
|
||||
// For use in patterns
|
||||
def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$dst),
|
||||
def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst),
|
||||
(ins VSrc_64:$src0, VSrc_64:$src1, SSrc_64:$src2), "", []
|
||||
>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
|
||||
// 64-bit vector move instruction. This is mainly used by the SIFoldOperands
|
||||
// pass to enable folding of inline immediates.
|
||||
def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$dst), (ins VSrc_64:$src0), "", []>;
|
||||
def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$vdst), (ins VSrc_64:$src0), "", []>;
|
||||
} // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0
|
||||
|
||||
let hasSideEffects = 1, SALU = 1 in {
|
||||
|
|
|
|||
|
|
@ -287,9 +287,9 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
|
|||
MachineInstrBuilder Inst32 =
|
||||
BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32));
|
||||
|
||||
// Add the dst operand if the 32-bit encoding also has an explicit $dst.
|
||||
// Add the dst operand if the 32-bit encoding also has an explicit $vdst.
|
||||
// For VOPC instructions, this is replaced by an implicit def of vcc.
|
||||
int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::dst);
|
||||
int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst);
|
||||
if (Op32DstIdx != -1) {
|
||||
// dst
|
||||
Inst32.addOperand(MI.getOperand(0));
|
||||
|
|
|
|||
|
|
@ -104,8 +104,7 @@ class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
|
|||
let Inst{51-32} = offset;
|
||||
}
|
||||
|
||||
class VOP3e_vi <bits<10> op> : Enc64 {
|
||||
bits<8> vdst;
|
||||
class VOP3a_vi <bits<10> op> : Enc64 {
|
||||
bits<2> src0_modifiers;
|
||||
bits<9> src0;
|
||||
bits<2> src1_modifiers;
|
||||
|
|
@ -115,7 +114,6 @@ class VOP3e_vi <bits<10> op> : Enc64 {
|
|||
bits<1> clamp;
|
||||
bits<2> omod;
|
||||
|
||||
let Inst{7-0} = vdst;
|
||||
let Inst{8} = src0_modifiers{1};
|
||||
let Inst{9} = src1_modifiers{1};
|
||||
let Inst{10} = src2_modifiers{1};
|
||||
|
|
@ -131,6 +129,20 @@ class VOP3e_vi <bits<10> op> : Enc64 {
|
|||
let Inst{63} = src2_modifiers{0};
|
||||
}
|
||||
|
||||
class VOP3e_vi <bits<10> op> : VOP3a_vi <op> {
|
||||
bits<8> vdst;
|
||||
|
||||
let Inst{7-0} = vdst;
|
||||
}
|
||||
|
||||
// Encoding used for VOPC instructions encoded as VOP3
|
||||
// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
|
||||
class VOP3ce_vi <bits<10> op> : VOP3a_vi <op> {
|
||||
bits<8> sdst;
|
||||
|
||||
let Inst{7-0} = sdst;
|
||||
}
|
||||
|
||||
class VOP3be_vi <bits<10> op> : Enc64 {
|
||||
bits<8> vdst;
|
||||
bits<2> src0_modifiers;
|
||||
|
|
@ -183,21 +195,21 @@ class VOP_DPPe : Enc64 {
|
|||
}
|
||||
|
||||
class VOP1_DPPe <bits<8> op> : VOP_DPPe {
|
||||
bits<8> dst;
|
||||
bits<8> vdst;
|
||||
|
||||
let Inst{8-0} = 0xfa; // dpp
|
||||
let Inst{16-9} = op;
|
||||
let Inst{24-17} = dst;
|
||||
let Inst{24-17} = vdst;
|
||||
let Inst{31-25} = 0x3f; //encoding
|
||||
}
|
||||
|
||||
class VOP2_DPPe <bits<6> op> : Enc32 {
|
||||
bits<8> dst;
|
||||
bits<8> vdst;
|
||||
bits<8> src1;
|
||||
|
||||
let Inst{8-0} = 0xfa; //dpp
|
||||
let Inst{16-9} = src1;
|
||||
let Inst{24-17} = dst;
|
||||
let Inst{24-17} = vdst;
|
||||
let Inst{30-25} = op;
|
||||
let Inst{31} = 0x0; //encoding
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue