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[GlobalISel] Add IR translation support for the @llvm.log10 intrinsic 

This adds IR translation support for @llvm.log10 and updates relevant tests.

https://reviews.llvm.org/D55392

llvm-svn: 348657
This commit is contained in:
Jessica Paquette 2018-12-07 22:08:02 +00:00
parent 2f5fd174c9
commit cc4b6920b3
5 changed files with 28 additions and 0 deletions
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3
llvm/include/llvm/Support/TargetOpcodes.def
View File

@ -454,6 +454,9 @@ HANDLE_TARGET_OPCODE(G_FLOG)
/// Floating point base-2 logarithm of a value.
HANDLE_TARGET_OPCODE(G_FLOG2)
/// Floating point base-10 logarithm of a value.
HANDLE_TARGET_OPCODE(G_FLOG10)
/// Generic FP negation.
HANDLE_TARGET_OPCODE(G_FNEG)

7
llvm/include/llvm/Target/GenericOpcodes.td
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@ -540,6 +540,13 @@ def G_FLOG2 : GenericInstruction {
let hasSideEffects = 0;
}
// Floating point base-10 logarithm of a value.
def G_FLOG10 : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
let hasSideEffects = 0;
}
//------------------------------------------------------------------------------
// Opcodes for LLVM Intrinsics
//------------------------------------------------------------------------------

5
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
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@ -895,6 +895,11 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::log10:
MIRBuilder.buildInstr(TargetOpcode::G_FLOG10)
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::fabs:
MIRBuilder.buildInstr(TargetOpcode::G_FABS)
.addDef(getOrCreateVReg(CI))

10
llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
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@ -1396,6 +1396,16 @@ define float @test_log2_intrin(float %a) {
ret float %res
}
declare float @llvm.log10.f32(float)
define float @test_log10_intrin(float %a) {
; CHECK-LABEL: name: test_log10_intrin
; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG10 [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call float @llvm.log10.f32(float %a)
ret float %res
}
declare float @llvm.fabs.f32(float)
define float @test_fabs_intrin(float %a) {
; CHECK-LABEL: name: test_fabs_intrin

3
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
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@ -267,6 +267,9 @@
# DEBUG-NEXT: G_FLOG2 (opcode {{[0-9]+}}): 1 type index
# DEBUG: .. type index coverage check SKIPPED: no rules defined
#
# DEBUG-NEXT: G_FLOG10 (opcode {{[0-9]+}}): 1 type index
# DEBUG: .. type index coverage check SKIPPED: no rules defined
#
# DEBUG-NEXT: G_FNEG (opcode {{[0-9]+}}): 1 type index
# DEBUG: .. type index coverage check SKIPPED: no rules defined
#