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Fixed a bug in splitting Scatter operation in the Type Legalizer. 

After the split of the Scatter operation, the order of the new instructions is well defined - Lo goes before Hi. Otherwise the semantic of Scatter (from LSB to MSB) is broken.
I'm chaining 2 nodes to prevent reordering.

Differential Revision https://reviews.llvm.org/D37670

llvm-svn: 312894
This commit is contained in:
Elena Demikhovsky 2017-09-11 06:18:15 +00:00
parent 70a6929f1a
commit cc477bbcea
2 changed files with 9 additions and 11 deletions
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11
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -1970,13 +1970,12 @@ SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
MachineMemOperand::MOStore, HiMemVT.getStoreSize(), MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
Alignment, N->getAAInfo(), N->getRanges()); Alignment, N->getAAInfo(), N->getRanges());
SDValue OpsHi[] = {Ch, DataHi, MaskHi, Ptr, IndexHi}; // The order of the Scatter operation after split is well defined. The "Hi"
Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(), // part comes after the "Lo". So these two operations should be chained one
// after another.
SDValue OpsHi[] = {Lo, DataHi, MaskHi, Ptr, IndexHi};
return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
DL, OpsHi, MMO); DL, OpsHi, MMO);
// Build a factor node to remember that this store is independent of the
// other one.
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
} }
SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {

7
llvm/test/CodeGen/X86/scatter-schedule.ll
View File

@ -5,16 +5,15 @@ target triple = "x86_64-unknown-linux-gnu"
; This test checks the order of scatter operations after split. ; This test checks the order of scatter operations after split.
; The right order is "from LSB to MSB", otherwise the semantic is broken. ; The right order is "from LSB to MSB", otherwise the semantic is broken.
; The submitted version of the test demonstrates the bug.
define void @test(i64 %x272, <16 x i32*> %x335, <16 x i32> %x270) { define void @test(i64 %x272, <16 x i32*> %x335, <16 x i32> %x270) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: vextracti64x4 $1, %zmm2, %ymm3
; CHECK-NEXT: kxnorw %k0, %k0, %k1 ; CHECK-NEXT: kxnorw %k0, %k0, %k1
; CHECK-NEXT: kxnorw %k0, %k0, %k2 ; CHECK-NEXT: kxnorw %k0, %k0, %k2
; CHECK-NEXT: vpscatterqd %ymm3, (,%zmm1) {%k2} ; CHECK-NEXT: vpscatterqd %ymm2, (,%zmm0) {%k2}
; CHECK-NEXT: vpscatterqd %ymm2, (,%zmm0) {%k1} ; CHECK-NEXT: vextracti64x4 $1, %zmm2, %ymm0
; CHECK-NEXT: vpscatterqd %ymm0, (,%zmm1) {%k1}
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> %x270, <16 x i32*> %x335, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>) call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> %x270, <16 x i32*> %x335, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)