forked from OSchip/llvm-project
Change VST1 instructions for loading Q register values to operate on pairs
of D registers. Add a separate VST1q instruction with a Q register source operand for use by storeRegToStackSlot. llvm-svn: 99265
This commit is contained in:
Bob Wilson
parent
3f7842232e
commit
cc0a2a75a0
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@ -738,7 +738,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
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// FIXME: Neon instructions should support predicates
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if (Align >= 16 && (getRegisterInfo().canRealignStack(MF))) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
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.addFrameIndex(FI).addImm(128)
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.addMemOperand(MMO)
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.addReg(SrcReg, getKillRegState(isKill)));
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@ -132,9 +132,9 @@ private:
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unsigned *QOpcodes0, unsigned *QOpcodes1);
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/// SelectVST - Select NEON store intrinsics. NumVecs should
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/// be 2, 3 or 4. The opcode arrays specify the instructions used for
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/// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
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/// stores of D registers and even subregs and odd subregs of Q registers.
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/// For NumVecs == 2, QOpcodes1 is not used.
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/// For NumVecs <= 2, QOpcodes1 is not used.
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SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
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unsigned *QOpcodes0, unsigned *QOpcodes1);
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@ -1048,7 +1048,7 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
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case MVT::v4f32:
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case MVT::v4i32: OpcodeIndex = 2; break;
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case MVT::v2i64: OpcodeIndex = 3;
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assert(NumVecs == 1 && "v2i64 type only supported for VLD1/VST1");
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assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
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break;
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}
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@ -1112,7 +1112,7 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
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SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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unsigned *DOpcodes, unsigned *QOpcodes0,
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unsigned *QOpcodes1) {
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assert(NumVecs >=2 && NumVecs <= 4 && "VST NumVecs out-of-range");
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assert(NumVecs >=1 && NumVecs <= 4 && "VST NumVecs out-of-range");
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DebugLoc dl = N->getDebugLoc();
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SDValue MemAddr, Align;
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@ -1137,6 +1137,9 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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case MVT::v8i16: OpcodeIndex = 1; break;
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case MVT::v4f32:
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case MVT::v4i32: OpcodeIndex = 2; break;
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case MVT::v2i64: OpcodeIndex = 3;
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assert(NumVecs == 1 && "v2i64 type only supported for VST1");
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break;
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}
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SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
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@ -1157,9 +1160,9 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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}
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EVT RegVT = GetNEONSubregVT(VT);
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if (NumVecs == 2) {
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// Quad registers are directly supported for VST2,
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// storing 2 pairs of D regs.
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if (NumVecs <= 2) {
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// Quad registers are directly supported for VST1 and VST2,
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// storing pairs of D regs.
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unsigned Opc = QOpcodes0[OpcodeIndex];
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
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@ -1170,7 +1173,8 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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Ops.push_back(Pred);
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Ops.push_back(Reg0); // predicate register
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Ops.push_back(Chain);
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 9);
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(),
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5 + 2 * NumVecs);
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}
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// Otherwise, quad registers are stored with two separate instructions,
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@ -1894,9 +1898,17 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vst1: {
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unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
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ARM::VST1d32, ARM::VST1d64 };
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unsigned QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
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ARM::VST1q32, ARM::VST1q64 };
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return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
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}
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case Intrinsic::arm_neon_vst2: {
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unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
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ARM::VST2d32, ARM::VST2d64 };
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ARM::VST2d32, ARM::VST1q64 };
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unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
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return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
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}
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@ -141,6 +141,7 @@ def VLD1q_UPD
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} // mayLoad = 1
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// Use vstmia to store a Q register as a D register pair.
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// This is equivalent to VSTMD except that it has a Q register operand.
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def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem,
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"vstmia", "$addr, ${src:dregpair}",
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[(store (v2f64 QPR:$src), addrmode4:$addr)]> {
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@ -151,6 +152,20 @@ def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem,
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let Inst{11-8} = 0b1011;
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}
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let mayStore = 1 in {
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// Use vst1 to store a Q register as a D register pair.
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// This alternative to VSTRQ allows an alignment to be specified.
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// This is equivalent to VST1q64 except that it has a Q register operand.
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def VST1q
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: NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src),
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IIC_VST, "vst1", "64", "${src:dregpair}, $addr", "", []>;
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def VST1q_UPD
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: NLdSt<0,0b00,0b1010,0b1100, (outs GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset, QPR:$src),
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IIC_VST, "vst1", "64", "{$src:dregpair}, $addr$offset",
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"$addr.addr = $wb", []>;
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} // mayStore = 1
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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// VLD1 : Vector Load (multiple single elements)
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@ -477,32 +492,27 @@ def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
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// FIXME: Not yet implemented.
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} // mayLoad = 1, hasExtraDefRegAllocReq = 1
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// VST1 : Vector Store (multiple single elements)
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class VST1D<bits<4> op7_4, string Dt, ValueType Ty>
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: NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
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"vst1", Dt, "\\{$src\\}, $addr", "",
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[(int_arm_neon_vst1 addrmode6:$addr, (Ty DPR:$src))]>;
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class VST1Q<bits<4> op7_4, string Dt, ValueType Ty>
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: NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
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"vst1", Dt, "${src:dregpair}, $addr", "",
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[(int_arm_neon_vst1 addrmode6:$addr, (Ty QPR:$src))]>;
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let hasExtraSrcRegAllocReq = 1 in {
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def VST1d8 : VST1D<0b0000, "8", v8i8>;
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def VST1d16 : VST1D<0b0100, "16", v4i16>;
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def VST1d32 : VST1D<0b1000, "32", v2i32>;
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def VST1df : VST1D<0b1000, "32", v2f32>;
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def VST1d64 : VST1D<0b1100, "64", v1i64>;
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def VST1q8 : VST1Q<0b0000, "8", v16i8>;
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def VST1q16 : VST1Q<0b0100, "16", v8i16>;
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def VST1q32 : VST1Q<0b1000, "32", v4i32>;
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def VST1qf : VST1Q<0b1000, "32", v4f32>;
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def VST1q64 : VST1Q<0b1100, "64", v2i64>;
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} // hasExtraSrcRegAllocReq
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
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// VST1 : Vector Store (multiple single elements)
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class VST1D<bits<4> op7_4, string Dt>
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: NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
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"vst1", Dt, "\\{$src\\}, $addr", "", []>;
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class VST1Q<bits<4> op7_4, string Dt>
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: NLdSt<0,0b00,0b1010,op7_4, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
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"vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
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def VST1d8 : VST1D<0b0000, "8">;
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def VST1d16 : VST1D<0b0100, "16">;
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def VST1d32 : VST1D<0b1000, "32">;
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def VST1d64 : VST1D<0b1100, "64">;
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def VST1q8 : VST1Q<0b0000, "8">;
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def VST1q16 : VST1Q<0b0100, "16">;
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def VST1q32 : VST1Q<0b1000, "32">;
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def VST1q64 : VST1Q<0b1100, "64">;
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// ...with address register writeback:
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class VST1DWB<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
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@ -582,9 +592,6 @@ class VST2Q<bits<4> op7_4, string Dt>
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def VST2d8 : VST2D<0b1000, 0b0000, "8">;
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def VST2d16 : VST2D<0b1000, 0b0100, "16">;
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def VST2d32 : VST2D<0b1000, 0b1000, "32">;
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def VST2d64 : NLdSt<0,0b00,0b1010,0b1100, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
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"vst1", "64", "\\{$src1, $src2\\}, $addr", "", []>;
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def VST2q8 : VST2Q<0b0000, "8">;
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def VST2q16 : VST2Q<0b0100, "16">;
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@ -606,11 +613,6 @@ class VST2QWB<bits<4> op7_4, string Dt>
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def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
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def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
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def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
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def VST2d64_UPD : NLdSt<0,0b00,0b1010,0b1100, (outs GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset,
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DPR:$src1, DPR:$src2), IIC_VST,
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"vst1", "64", "\\{$src1, $src2\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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def VST2q8_UPD : VST2QWB<0b0000, "8">;
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def VST2q16_UPD : VST2QWB<0b0100, "16">;
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@ -50,10 +50,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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case ARM::VLD1q16:
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case ARM::VLD1q32:
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case ARM::VLD1q64:
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FirstOpnd = 0;
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NumRegs = 2;
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return true;
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case ARM::VLD2d8:
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case ARM::VLD2d16:
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case ARM::VLD2d32:
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@ -177,10 +173,13 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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Stride = 2;
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return true;
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case ARM::VST1q8:
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case ARM::VST1q16:
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case ARM::VST1q32:
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case ARM::VST1q64:
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case ARM::VST2d8:
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case ARM::VST2d16:
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case ARM::VST2d32:
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case ARM::VST2d64:
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case ARM::VST2LNd8:
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case ARM::VST2LNd16:
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case ARM::VST2LNd32:
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