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[InstCombine] allow or(sext(A), B) --> A ? -1 : B transform for vectors 

llvm-svn: 274883
This commit is contained in:
Sanjay Patel 2016-07-08 17:01:15 +00:00
parent bc3b1f3b7b
commit cbfca9e8ef
2 changed files with 7 additions and 8 deletions
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9
llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
View File

@ -2393,11 +2393,12 @@ Instruction *InstCombiner::visitOr(BinaryOperator &I) {
if (Instruction *CastedOr = foldCastedBitwiseLogic(I)) if (Instruction *CastedOr = foldCastedBitwiseLogic(I))
return CastedOr; return CastedOr;
// or(sext(A), B) -> A ? -1 : B where A is an i1 // or(sext(A), B) / or(B, sext(A)) --> A ? -1 : B, where A is i1 or <N x i1>.
// or(A, sext(B)) -> B ? -1 : A where B is an i1 if (match(Op0, m_SExt(m_Value(A))) &&
if (match(Op0, m_SExt(m_Value(A))) && A->getType()->isIntegerTy(1)) A->getType()->getScalarType()->isIntegerTy(1))
return SelectInst::Create(A, ConstantInt::getSigned(I.getType(), -1), Op1); return SelectInst::Create(A, ConstantInt::getSigned(I.getType(), -1), Op1);
if (match(Op1, m_SExt(m_Value(A))) && A->getType()->isIntegerTy(1)) if (match(Op1, m_SExt(m_Value(A))) &&
A->getType()->getScalarType()->isIntegerTy(1))
return SelectInst::Create(A, ConstantInt::getSigned(I.getType(), -1), Op0); return SelectInst::Create(A, ConstantInt::getSigned(I.getType(), -1), Op0);
// Note: If we've gotten to the point of visiting the outer OR, then the // Note: If we've gotten to the point of visiting the outer OR, then the

6
llvm/test/Transforms/InstCombine/or.ll
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@ -447,8 +447,7 @@ define i32 @orsext_to_sel_swap(i32 %x, i1 %y) {
define <2 x i32> @orsext_to_sel_vec(<2 x i32> %x, <2 x i1> %y) { define <2 x i32> @orsext_to_sel_vec(<2 x i32> %x, <2 x i1> %y) {
; CHECK-LABEL: @orsext_to_sel_vec( ; CHECK-LABEL: @orsext_to_sel_vec(
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> %y to <2 x i32> ; CHECK-NEXT: [[OR:%.*]] = select <2 x i1> %y, <2 x i32> <i32 -1, i32 -1>, <2 x i32> %x
; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[SEXT]], %x
; CHECK-NEXT: ret <2 x i32> [[OR]] ; CHECK-NEXT: ret <2 x i32> [[OR]]
; ;
%sext = sext <2 x i1> %y to <2 x i32> %sext = sext <2 x i1> %y to <2 x i32>
@ -458,8 +457,7 @@ define <2 x i32> @orsext_to_sel_vec(<2 x i32> %x, <2 x i1> %y) {
define <2 x i132> @orsext_to_sel_vec_swap(<2 x i132> %x, <2 x i1> %y) { define <2 x i132> @orsext_to_sel_vec_swap(<2 x i132> %x, <2 x i1> %y) {
; CHECK-LABEL: @orsext_to_sel_vec_swap( ; CHECK-LABEL: @orsext_to_sel_vec_swap(
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> %y to <2 x i132> ; CHECK-NEXT: [[OR:%.*]] = select <2 x i1> %y, <2 x i132> <i132 -1, i132 -1>, <2 x i132> %x
; CHECK-NEXT: [[OR:%.*]] = or <2 x i132> [[SEXT]], %x
; CHECK-NEXT: ret <2 x i132> [[OR]] ; CHECK-NEXT: ret <2 x i132> [[OR]]
; ;
%sext = sext <2 x i1> %y to <2 x i132> %sext = sext <2 x i1> %y to <2 x i132>