forked from OSchip/llvm-project
[AArch64] Adjust the cost model for Exynos M1 and M2
Fix the modeling of loads and stores using the pre or post indexed addressing modes. llvm-svn: 318312
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@ -99,7 +99,8 @@ def M1WriteLC : SchedWriteRes<[M1UnitA,
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def M1WriteLD : SchedWriteRes<[M1UnitA,
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M1UnitL,
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M1UnitL]> { let Latency = 5; }
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def M1WriteLH : SchedWriteRes<[]> { let Latency = 5; }
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def M1WriteLH : SchedWriteRes<[]> { let Latency = 5;
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let NumMicroOps = 0; }
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def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
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SchedVar<NoSchedPred, [M1WriteA1,
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M1WriteL5]>]>;
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@ -159,12 +160,14 @@ def : WriteRes<WriteExtr, [M1UnitALU,
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M1UnitALU]> { let Latency = 2; }
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// Addressing modes.
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def : WriteRes<WriteAdr, []> { let Latency = 1; }
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def : WriteRes<WriteAdr, []> { let Latency = 1;
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let NumMicroOps = 0; }
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def : SchedAlias<ReadAdrBase, M1ReadAdrBase>;
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// Load instructions.
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def : WriteRes<WriteLD, [M1UnitL]> { let Latency = 4; }
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def : WriteRes<WriteLDHi, []> { let Latency = 4; }
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def : WriteRes<WriteLDHi, []> { let Latency = 4;
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let NumMicroOps = 0; }
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def : SchedAlias<WriteLDIdx, M1WriteLX>;
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// Store instructions.
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@ -432,31 +435,27 @@ def : InstRW<[M1WriteNEONI], (instregex "^FMOV[DS][WX](High)?r")>;
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def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>;
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def : InstRW<[WriteVLD], (instregex "^LDUR[BDHSQ]i")>;
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def : InstRW<[WriteVLD,
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WriteAdr,
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ReadAdrBase], (instregex "^LDR[BDHSQ](post|pre)")>;
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WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>;
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def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>;
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def : InstRW<[M1WriteLX,
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ReadAdrBase], (instregex "^LDR[BDHS]ro[WX]")>;
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def : InstRW<[M1WriteLC,
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ReadAdrBase], (instregex "^LDRQro[WX]")>;
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def : InstRW<[WriteVLD,
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M1WriteLH], (instregex "^LDN?P[DS]i")>;
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M1WriteLH], (instregex "^LDN?P[DS]i")>;
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def : InstRW<[M1WriteLB,
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M1WriteLH], (instregex "^LDN?PQi")>;
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M1WriteLH], (instregex "^LDN?PQi")>;
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def : InstRW<[M1WriteLC,
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M1WriteLH,
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WriteAdr,
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ReadAdrBase], (instregex "^LDP[DS](post|pre)")>;
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WriteAdr], (instregex "^LDP[DS](post|pre)")>;
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def : InstRW<[M1WriteLD,
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M1WriteLH,
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WriteAdr,
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ReadAdrBase], (instregex "^LDPQ(post|pre)")>;
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WriteAdr], (instregex "^LDPQ(post|pre)")>;
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// FP store instructions.
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def : InstRW<[WriteVST], (instregex "^STUR[BDHSQ]i")>;
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def : InstRW<[WriteVST,
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WriteAdr,
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ReadAdrBase], (instregex "^STR[BDHSQ](post|pre)")>;
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WriteAdr], (instregex "^STR[BDHSQ](post|pre)")>;
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def : InstRW<[WriteVST], (instregex "^STR[BDHSQ]ui")>;
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def : InstRW<[M1WriteSY,
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ReadAdrBase], (instregex "^STR[BDHS]ro[WX]")>;
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@ -464,11 +463,9 @@ def : InstRW<[M1WriteSB,
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ReadAdrBase], (instregex "^STRQro[WX]")>;
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def : InstRW<[WriteVST], (instregex "^STN?P[DSQ]i")>;
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def : InstRW<[WriteVST,
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WriteAdr,
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ReadAdrBase], (instregex "^STP[DS](post|pre)")>;
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WriteAdr], (instregex "^STP[DS](post|pre)")>;
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def : InstRW<[M1WriteSC,
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WriteAdr,
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ReadAdrBase], (instregex "^STPQ(post|pre)")>;
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WriteAdr], (instregex "^STPQ(post|pre)")>;
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// ASIMD instructions.
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def : InstRW<[M1WriteNMISC3], (instregex "^[SU]ABAL?v")>;
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