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[X86] Define __LAHF_SAHF__ if feature 'sahf' is set or 32-bit mode 

GCC 11 will define this macro.

In LLVM, the feature flag only applies to 64-bit mode and we always define the
macro in 32-bit mode. This is different from GCC -m32 in which -mno-sahf can
suppress the macro. The discrepancy can unlikely cause trouble.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D89198
This commit is contained in:
Fangrui Song 2020-10-10 22:21:47 -07:00
parent be6e8e50f4
commit cbe4d973ed
2 changed files with 17 additions and 0 deletions
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5
clang/lib/Basic/Targets/X86.cpp
View File

@ -560,6 +560,11 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
if (HasVPCLMULQDQ)
Builder.defineMacro("__VPCLMULQDQ__");
// Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
// the feature flag only applies to 64-bit mode.
if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
Builder.defineMacro("__LAHF_SAHF__");
if (HasLZCNT)
Builder.defineMacro("__LZCNT__");

12
clang/test/Preprocessor/predefined-arch-macros.c
View File

@ -3,6 +3,7 @@
// RUN: %clang -march=i386 -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I386_M32
// CHECK_I386_M32: #define __LAHF_SAHF__ 1
// CHECK_I386_M32: #define __i386 1
// CHECK_I386_M32: #define __i386__ 1
// CHECK_I386_M32: #define __tune_i386__ 1
@ -541,6 +542,7 @@
// CHECK_CORE_AVX2_M32: #define __F16C__ 1
// CHECK_CORE_AVX2_M32: #define __FMA__ 1
// CHECK_CORE_AVX2_M32: #define __INVPCID__ 1
// CHECK_CORE_AVX2_M32: #define __LAHF_SAHF__ 1
// CHECK_CORE_AVX2_M32: #define __LZCNT__ 1
// CHECK_CORE_AVX2_M32: #define __MMX__ 1
// CHECK_CORE_AVX2_M32: #define __MOVBE__ 1
@ -572,6 +574,7 @@
// CHECK_CORE_AVX2_M64: #define __F16C__ 1
// CHECK_CORE_AVX2_M64: #define __FMA__ 1
// CHECK_CORE_AVX2_M64: #define __INVPCID__ 1
// CHECK_CORE_AVX2_M64: #define __LAHF_SAHF__ 1
// CHECK_CORE_AVX2_M64: #define __LZCNT__ 1
// CHECK_CORE_AVX2_M64: #define __MMX__ 1
// CHECK_CORE_AVX2_M64: #define __MOVBE__ 1
@ -607,6 +610,7 @@
// CHECK_BROADWELL_M32: #define __F16C__ 1
// CHECK_BROADWELL_M32: #define __FMA__ 1
// CHECK_BROADWELL_M32: #define __INVPCID__ 1
// CHECK_BROADWELL_M32: #define __LAHF_SAHF__ 1
// CHECK_BROADWELL_M32: #define __LZCNT__ 1
// CHECK_BROADWELL_M32: #define __MMX__ 1
// CHECK_BROADWELL_M32: #define __MOVBE__ 1
@ -641,6 +645,7 @@
// CHECK_BROADWELL_M64: #define __F16C__ 1
// CHECK_BROADWELL_M64: #define __FMA__ 1
// CHECK_BROADWELL_M64: #define __INVPCID__ 1
// CHECK_BROADWELL_M64: #define __LAHF_SAHF__ 1
// CHECK_BROADWELL_M64: #define __LZCNT__ 1
// CHECK_BROADWELL_M64: #define __MMX__ 1
// CHECK_BROADWELL_M64: #define __MOVBE__ 1
@ -2515,6 +2520,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_AMDFAM10_M32
// CHECK_AMDFAM10_M32: #define __3dNOW_A__ 1
// CHECK_AMDFAM10_M32: #define __3dNOW__ 1
// CHECK_AMDFAM10_M32: #define __LAHF_SAHF__ 1
// CHECK_AMDFAM10_M32: #define __LZCNT__ 1
// CHECK_AMDFAM10_M32: #define __MMX__ 1
// CHECK_AMDFAM10_M32: #define __POPCNT__ 1
@ -2538,6 +2544,7 @@
// CHECK_AMDFAM10_M64: #define __3dNOW_A__ 1
// CHECK_AMDFAM10_M64: #define __3dNOW__ 1
// CHECK_AMDFAM10_M64: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
// CHECK_AMDFAM10_M64: #define __LAHF_SAHF__ 1
// CHECK_AMDFAM10_M64: #define __LZCNT__ 1
// CHECK_AMDFAM10_M64: #define __MMX__ 1
// CHECK_AMDFAM10_M64: #define __POPCNT__ 1
@ -2562,6 +2569,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BTVER1_M32
// CHECK_BTVER1_M32-NOT: #define __3dNOW_A__ 1
// CHECK_BTVER1_M32-NOT: #define __3dNOW__ 1
// CHECK_BTVER1_M32: #define __LAHF_SAHF__ 1
// CHECK_BTVER1_M32: #define __LZCNT__ 1
// CHECK_BTVER1_M32: #define __MMX__ 1
// CHECK_BTVER1_M32: #define __POPCNT__ 1
@ -2584,6 +2592,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BTVER1_M64
// CHECK_BTVER1_M64-NOT: #define __3dNOW_A__ 1
// CHECK_BTVER1_M64-NOT: #define __3dNOW__ 1
// CHECK_BTVER1_M64: #define __LAHF_SAHF__ 1
// CHECK_BTVER1_M64: #define __LZCNT__ 1
// CHECK_BTVER1_M64: #define __MMX__ 1
// CHECK_BTVER1_M64: #define __POPCNT__ 1
@ -3023,6 +3032,7 @@
// CHECK_ZNVER1_M64-NOT: #define __FMA4__ 1
// CHECK_ZNVER1_M64: #define __FMA__ 1
// CHECK_ZNVER1_M64: #define __FSGSBASE__ 1
// CHECK_ZNVER1_M64: #define __LAHF_SAHF__ 1
// CHECK_ZNVER1_M64: #define __LZCNT__ 1
// CHECK_ZNVER1_M64: #define __MMX__ 1
// CHECK_ZNVER1_M64: #define __MOVBE__ 1
@ -3073,6 +3083,7 @@
// CHECK_ZNVER2_M32-NOT: #define __FMA4__ 1
// CHECK_ZNVER2_M32: #define __FMA__ 1
// CHECK_ZNVER2_M32: #define __FSGSBASE__ 1
// CHECK_ZNVER2_M32: #define __LAHF_SAHF__ 1
// CHECK_ZNVER2_M32: #define __LZCNT__ 1
// CHECK_ZNVER2_M32: #define __MMX__ 1
// CHECK_ZNVER2_M32: #define __PCLMUL__ 1
@ -3122,6 +3133,7 @@
// CHECK_ZNVER2_M64-NOT: #define __FMA4__ 1
// CHECK_ZNVER2_M64: #define __FMA__ 1
// CHECK_ZNVER2_M64: #define __FSGSBASE__ 1
// CHECK_ZNVER2_M64: #define __LAHF_SAHF__ 1
// CHECK_ZNVER2_M64: #define __LZCNT__ 1
// CHECK_ZNVER2_M64: #define __MMX__ 1
// CHECK_ZNVER2_M64: #define __PCLMUL__ 1