[AArch64][SVE] Asm: Support for predicated unary operations.

The patch includes support for the following instructions:

       ABS z0.h, p0/m, z0.h
       NEG z0.h, p0/m, z0.h

  (S|U)XTB z0.h, p0/m, z0.h
  (S|U)XTB z0.s, p0/m, z0.s
  (S|U)XTB z0.d, p0/m, z0.d

  (S|U)XTH z0.s, p0/m, z0.s
  (S|U)XTH z0.d, p0/m, z0.d

  (S|U)XTW z0.d, p0/m, z0.d

llvm-svn: 336204
This commit is contained in:
Sander de Smalen 2018-07-03 14:57:48 +00:00
parent 9338a8838a
commit cbd224941f
15 changed files with 557 additions and 0 deletions

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@ -43,6 +43,15 @@ let Predicates = [HasSVE] in {
defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">;
defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">;
defm SXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b000, "sxtb">;
defm UXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b001, "uxtb">;
defm SXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b010, "sxth">;
defm UXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b011, "uxth">;
defm SXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b100, "sxtw">;
defm UXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b101, "uxtw">;
defm ABS_ZPmZ : sve_int_un_pred_arit_0< 0b110, "abs">;
defm NEG_ZPmZ : sve_int_un_pred_arit_0< 0b111, "neg">;
defm FADD_ZPmI : sve_fp_2op_i_p_zds<0b000, "fadd", sve_fpimm_half_one>;
defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>;
defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>;

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@ -887,6 +887,54 @@ multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> {
def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>;
}
//===----------------------------------------------------------------------===//
// SVE Integer Arithmetic - Unary Predicated Group
//===----------------------------------------------------------------------===//
class sve_int_un_pred_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
asm, "\t$Zd, $Pg/m, $Zn",
"",
[]>, Sched<[]> {
bits<3> Pg;
bits<5> Zd;
bits<5> Zn;
let Inst{31-24} = 0b00000100;
let Inst{23-22} = sz8_64;
let Inst{21-19} = 0b010;
let Inst{18-16} = opc;
let Inst{15-13} = 0b101;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd";
}
multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm> {
def _B : sve_int_un_pred_arit_0<0b00, opc, asm, ZPR8>;
def _H : sve_int_un_pred_arit_0<0b01, opc, asm, ZPR16>;
def _S : sve_int_un_pred_arit_0<0b10, opc, asm, ZPR32>;
def _D : sve_int_un_pred_arit_0<0b11, opc, asm, ZPR64>;
}
multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm> {
def _H : sve_int_un_pred_arit_0<0b01, opc, asm, ZPR16>;
def _S : sve_int_un_pred_arit_0<0b10, opc, asm, ZPR32>;
def _D : sve_int_un_pred_arit_0<0b11, opc, asm, ZPR64>;
}
multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm> {
def _S : sve_int_un_pred_arit_0<0b10, opc, asm, ZPR32>;
def _D : sve_int_un_pred_arit_0<0b11, opc, asm, ZPR64>;
}
multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm> {
def _D : sve_int_un_pred_arit_0<0b11, opc, asm, ZPR64>;
}
//===----------------------------------------------------------------------===//
// SVE Integer Wide Immediate - Unpredicated Group
//===----------------------------------------------------------------------===//

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@ -0,0 +1,36 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Element size specifiers should match.
abs z0.h, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: abs z0.h, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Missing predicate suffix
abs z29.d, p7, z29.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: abs z29.d, p7, z29.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
abs z0.b, p8/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: abs z0.b, p8/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
abs z0.h, p8/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: abs z0.h, p8/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
abs z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: abs z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
abs z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: abs z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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@ -0,0 +1,56 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
abs z0.b, p0/m, z0.b
// CHECK-INST: abs z0.b, p0/m, z0.b
// CHECK-ENCODING: [0x00,0xa0,0x16,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 16 04 <unknown>
abs z0.h, p0/m, z0.h
// CHECK-INST: abs z0.h, p0/m, z0.h
// CHECK-ENCODING: [0x00,0xa0,0x56,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 56 04 <unknown>
abs z0.s, p0/m, z0.s
// CHECK-INST: abs z0.s, p0/m, z0.s
// CHECK-ENCODING: [0x00,0xa0,0x96,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 96 04 <unknown>
abs z0.d, p0/m, z0.d
// CHECK-INST: abs z0.d, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd6,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d6 04 <unknown>
abs z31.b, p7/m, z31.b
// CHECK-INST: abs z31.b, p7/m, z31.b
// CHECK-ENCODING: [0xff,0xbf,0x16,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 16 04 <unknown>
abs z31.h, p7/m, z31.h
// CHECK-INST: abs z31.h, p7/m, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x56,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 56 04 <unknown>
abs z31.s, p7/m, z31.s
// CHECK-INST: abs z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x96,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 96 04 <unknown>
abs z31.d, p7/m, z31.d
// CHECK-INST: abs z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd6,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d6 04 <unknown>

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@ -0,0 +1,36 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Element size specifiers should match.
neg z0.h, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: neg z0.h, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Missing predicate suffix
neg z29.d, p7, z29.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: neg z29.d, p7, z29.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
neg z0.b, p8/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: neg z0.b, p8/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
neg z0.h, p8/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: neg z0.h, p8/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
neg z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: neg z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
neg z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: neg z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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@ -0,0 +1,56 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
neg z0.b, p0/m, z0.b
// CHECK-INST: neg z0.b, p0/m, z0.b
// CHECK-ENCODING: [0x00,0xa0,0x17,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 17 04 <unknown>
neg z0.h, p0/m, z0.h
// CHECK-INST: neg z0.h, p0/m, z0.h
// CHECK-ENCODING: [0x00,0xa0,0x57,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 57 04 <unknown>
neg z0.s, p0/m, z0.s
// CHECK-INST: neg z0.s, p0/m, z0.s
// CHECK-ENCODING: [0x00,0xa0,0x97,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 97 04 <unknown>
neg z0.d, p0/m, z0.d
// CHECK-INST: neg z0.d, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd7,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d7 04 <unknown>
neg z31.b, p7/m, z31.b
// CHECK-INST: neg z31.b, p7/m, z31.b
// CHECK-ENCODING: [0xff,0xbf,0x17,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 17 04 <unknown>
neg z31.h, p7/m, z31.h
// CHECK-INST: neg z31.h, p7/m, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x57,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 57 04 <unknown>
neg z31.s, p7/m, z31.s
// CHECK-INST: neg z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x97,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 97 04 <unknown>
neg z31.d, p7/m, z31.d
// CHECK-INST: neg z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd7,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d7 04 <unknown>

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@ -0,0 +1,41 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Element size specifiers should match.
sxtb z0.d, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sxtb z0.d, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Missing predicate suffix
sxtb z29.d, p7, z29.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sxtb z29.d, p7, z29.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Unsupported element widths
sxtb z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sxtb z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
sxtb z0.h, p8/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sxtb z0.h, p8/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sxtb z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sxtb z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sxtb z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sxtb z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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@ -0,0 +1,44 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sxtb z0.h, p0/m, z0.h
// CHECK-INST: sxtb z0.h, p0/m, z0.h
// CHECK-ENCODING: [0x00,0xa0,0x50,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 50 04 <unknown>
sxtb z0.s, p0/m, z0.s
// CHECK-INST: sxtb z0.s, p0/m, z0.s
// CHECK-ENCODING: [0x00,0xa0,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 90 04 <unknown>
sxtb z0.d, p0/m, z0.d
// CHECK-INST: sxtb z0.d, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d0 04 <unknown>
sxtb z31.h, p7/m, z31.h
// CHECK-INST: sxtb z31.h, p7/m, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x50,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 50 04 <unknown>
sxtb z31.s, p7/m, z31.s
// CHECK-INST: sxtb z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 90 04 <unknown>
sxtb z31.d, p7/m, z31.d
// CHECK-INST: sxtb z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d0 04 <unknown>

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@ -0,0 +1,41 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Element size specifiers should match.
sxth z0.d, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sxth z0.d, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Missing predicate suffix
sxth z29.d, p7, z29.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sxth z29.d, p7, z29.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Unsupported element widths
sxth z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sxth z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sxth z0.h, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sxth z0.h, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
sxth z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sxth z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sxth z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sxth z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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@ -0,0 +1,32 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sxth z0.s, p0/m, z0.s
// CHECK-INST: sxth z0.s, p0/m, z0.s
// CHECK-ENCODING: [0x00,0xa0,0x92,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 92 04 <unknown>
sxth z0.d, p0/m, z0.d
// CHECK-INST: sxth z0.d, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd2,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d2 04 <unknown>
sxth z31.s, p7/m, z31.s
// CHECK-INST: sxth z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x92,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 92 04 <unknown>
sxth z31.d, p7/m, z31.d
// CHECK-INST: sxth z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd2,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d2 04 <unknown>

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@ -0,0 +1,42 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Element size specifiers should match.
sxtw z0.d, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sxtw z0.d, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Missing predicate suffix
sxtw z29.d, p7, z29.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sxtw z29.d, p7, z29.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Unsupported element widths
sxtw z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sxtw z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sxtw z0.h, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sxtw z0.h, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sxtw z0.s, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sxtw z0.s, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
sxtw z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sxtw z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sxtw z0.d, p0/m, z0.d
// CHECK-INST: sxtw z0.d, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd4,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d4 04 <unknown>
sxtw z31.d, p7/m, z31.d
// CHECK-INST: sxtw z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd4,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d4 04 <unknown>

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uxtb z0.h, p0/m, z0.h
// CHECK-INST: uxtb z0.h, p0/m, z0.h
// CHECK-ENCODING: [0x00,0xa0,0x51,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 51 04 <unknown>
uxtb z0.s, p0/m, z0.s
// CHECK-INST: uxtb z0.s, p0/m, z0.s
// CHECK-ENCODING: [0x00,0xa0,0x91,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 91 04 <unknown>
uxtb z0.d, p0/m, z0.d
// CHECK-INST: uxtb z0.d, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd1,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d1 04 <unknown>
uxtb z31.h, p7/m, z31.h
// CHECK-INST: uxtb z31.h, p7/m, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x51,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 51 04 <unknown>
uxtb z31.s, p7/m, z31.s
// CHECK-INST: uxtb z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x91,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 91 04 <unknown>
uxtb z31.d, p7/m, z31.d
// CHECK-INST: uxtb z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd1,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d1 04 <unknown>

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uxth z0.s, p0/m, z0.s
// CHECK-INST: uxth z0.s, p0/m, z0.s
// CHECK-ENCODING: [0x00,0xa0,0x93,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 93 04 <unknown>
uxth z0.d, p0/m, z0.d
// CHECK-INST: uxth z0.d, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd3,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d3 04 <unknown>
uxth z31.s, p7/m, z31.s
// CHECK-INST: uxth z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x93,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 93 04 <unknown>
uxth z31.d, p7/m, z31.d
// CHECK-INST: uxth z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd3,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d3 04 <unknown>

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uxtw z0.d, p0/m, z0.d
// CHECK-INST: uxtw z0.d, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0xd5,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 d5 04 <unknown>
uxtw z31.d, p7/m, z31.d
// CHECK-INST: uxtw z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xd5,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf d5 04 <unknown>