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[AArch64] Teach RegisterBankInfo about the mapping of register classes 

on register banks.

llvm-svn: 265626
This commit is contained in:
Quentin Colombet 2016-04-07 00:14:30 +00:00
parent 56ad4048ae
commit cbc353a422
2 changed files with 50 additions and 0 deletions
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35
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
View File

@ -63,3 +63,38 @@ unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,
// * build_sequence cost.
return 0;
}
const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass(
const TargetRegisterClass &RC) const {
switch (RC.getID()) {
case AArch64::FPR8RegClassID:
case AArch64::FPR16RegClassID:
case AArch64::FPR32RegClassID:
case AArch64::FPR64RegClassID:
case AArch64::FPR128RegClassID:
case AArch64::FPR128_loRegClassID:
case AArch64::DDRegClassID:
case AArch64::DDDRegClassID:
case AArch64::DDDDRegClassID:
case AArch64::QQRegClassID:
case AArch64::QQQRegClassID:
case AArch64::QQQQRegClassID:
return getRegBank(AArch64::FPRRegBankID);
case AArch64::GPR32commonRegClassID:
case AArch64::GPR32RegClassID:
case AArch64::GPR32spRegClassID:
case AArch64::GPR32sponlyRegClassID:
case AArch64::GPR32allRegClassID:
case AArch64::GPR64commonRegClassID:
case AArch64::GPR64RegClassID:
case AArch64::GPR64spRegClassID:
case AArch64::GPR64sponlyRegClassID:
case AArch64::GPR64allRegClassID:
case AArch64::tcGPR64RegClassID:
case AArch64::WSeqPairsClassRegClassID:
case AArch64::XSeqPairsClassRegClassID:
return getRegBank(AArch64::FPRRegBankID);
default:
llvm_unreachable("Register class not supported");
}
}

15
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h
View File

@ -36,6 +36,21 @@ public:
/// get the cost of A = COPY B.
unsigned copyCost(const RegisterBank &A,
const RegisterBank &B) const override;
/// Get a register bank that covers \p RC.
///
/// \pre \p RC is a user-defined register class (as opposed as one
/// generated by TableGen).
///
/// \note The mapping RC -> RegBank could be built while adding the
/// coverage for the register banks. However, we do not do it, because,
/// at least for now, we only need this information for register classes
/// that are used in the description of instruction. In other words,
/// there are just a handful of them and we do not want to waste space.
///
/// \todo This should be TableGen'ed.
const RegisterBank &
getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
};
} // End llvm namespace.
#endif