forked from OSchip/llvm-project
parent
2cfce18645
commit
cb8fa3ec1d
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@ -182,7 +182,7 @@ def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
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def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.7 Pairdise Addition
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// E.3.7 Pairwise Addition
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def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">;
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def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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@ -352,7 +352,7 @@ def VEXT : WInst<"vext", "dddi",
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"cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">;
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////////////////////////////////////////////////////////////////////////////////
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// E.3.27 Reverse vector elements (sdap endianness)
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// E.3.27 Reverse vector elements
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def VREV64 : Inst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",
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OP_REV64>;
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def VREV32 : Inst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;
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