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add a note, from PR5100 

llvm-svn: 96490
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Chris Lattner 2010-02-17 18:42:24 +00:00
parent df048a962b
commit cb80e2527e
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llvm/lib/Target/ARM/README.txt
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@ -10,6 +10,8 @@ Reimplement 'select' in terms of 'SEL'.
* Implement pre/post increment support. (e.g. PR935) * Implement pre/post increment support. (e.g. PR935)
* Implement smarter constant generation for binops with large immediates. * Implement smarter constant generation for binops with large immediates.
A few ARMv6T2 ops should be pattern matched: BFI, SBFX, and UBFX
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
Crazy idea: Consider code that uses lots of 8-bit or 16-bit values. By the Crazy idea: Consider code that uses lots of 8-bit or 16-bit values. By the