forked from OSchip/llvm-project
[ARM] Extra MVE constant select test. NFC
This commit is contained in:
David Green
parent
93e1802af3
commit
cb62c3761f
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@ -0,0 +1,188 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_C1_or_C2_vec:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: adr r0, .LCPI0_0
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; CHECK-NEXT: adr r1, .LCPI0_1
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; CHECK-NEXT: vcmp.i32 eq, q0, q1
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; CHECK-NEXT: vldrw.u32 q0, [r1]
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .long 3000 @ 0xbb8
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 4294967295 @ 0xffffffff
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .LCPI0_1:
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; CHECK-NEXT: .long 42 @ 0x2a
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 4294967294 @ 0xfffffffe
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; CHECK-NEXT: .long 4294967295 @ 0xffffffff
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
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ret <4 x i32> %add
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}
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define arm_aapcs_vfpcc <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: adr r0, .LCPI1_0
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; CHECK-NEXT: adr r1, .LCPI1_1
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; CHECK-NEXT: vcmp.i32 eq, q0, q1
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; CHECK-NEXT: vldrw.u32 q0, [r1]
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI1_0:
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; CHECK-NEXT: .long 43 @ 0x2b
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 4294967295 @ 0xffffffff
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .LCPI1_1:
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; CHECK-NEXT: .long 42 @ 0x2a
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 4294967294 @ 0xfffffffe
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; CHECK-NEXT: .long 4294967295 @ 0xffffffff
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
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ret <4 x i32> %add
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}
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define arm_aapcs_vfpcc <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: adr r0, .LCPI2_0
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; CHECK-NEXT: adr r1, .LCPI2_1
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; CHECK-NEXT: vcmp.i32 eq, q0, q1
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; CHECK-NEXT: vldrw.u32 q0, [r1]
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI2_0:
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; CHECK-NEXT: .long 43 @ 0x2b
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 4294967295 @ 0xffffffff
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .LCPI2_1:
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; CHECK-NEXT: .long 44 @ 0x2c
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; CHECK-NEXT: .long 2 @ 0x2
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 1 @ 0x1
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
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ret <4 x i32> %add
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}
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define arm_aapcs_vfpcc <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_minus1_or_0_vec:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vmov.i8 q3, #0xff
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; CHECK-NEXT: vcmp.i32 eq, q0, q1
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; CHECK-NEXT: vpsel q0, q3, q2
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; CHECK-NEXT: bx lr
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %add
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}
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define arm_aapcs_vfpcc <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_0_or_minus1_vec:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i8 q2, #0xff
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; CHECK-NEXT: vmov.i32 q3, #0x0
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; CHECK-NEXT: vcmp.i32 eq, q0, q1
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; CHECK-NEXT: vpsel q0, q3, q2
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; CHECK-NEXT: bx lr
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %add
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}
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define arm_aapcs_vfpcc <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_1_or_0_vec:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vmov.i32 q3, #0x1
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; CHECK-NEXT: vcmp.i32 eq, q0, q1
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; CHECK-NEXT: vpsel q0, q3, q2
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; CHECK-NEXT: bx lr
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %add
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}
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define arm_aapcs_vfpcc <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_0_or_1_vec:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q2, #0x1
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; CHECK-NEXT: vmov.i32 q3, #0x0
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; CHECK-NEXT: vcmp.i32 eq, q0, q1
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; CHECK-NEXT: vpsel q0, q3, q2
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; CHECK-NEXT: bx lr
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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define arm_aapcs_vfpcc <16 x i8> @signbit_mask_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: signbit_mask_v16i8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vcmp.s8 lt, q0, zr
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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%cond = icmp slt <16 x i8> %a, zeroinitializer
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%r = select <16 x i1> %cond, <16 x i8> %b, <16 x i8> zeroinitializer
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ret <16 x i8> %r
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}
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define arm_aapcs_vfpcc <8 x i16> @signbit_mask_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: signbit_mask_v8i16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vcmp.s16 lt, q0, zr
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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%cond = icmp slt <8 x i16> %a, zeroinitializer
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%r = select <8 x i1> %cond, <8 x i16> %b, <8 x i16> zeroinitializer
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ret <8 x i16> %r
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}
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define arm_aapcs_vfpcc <4 x i32> @signbit_mask_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: signbit_mask_v4i32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vcmp.s32 lt, q0, zr
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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%cond = icmp slt <4 x i32> %a, zeroinitializer
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%r = select <4 x i1> %cond, <4 x i32> %b, <4 x i32> zeroinitializer
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ret <4 x i32> %r
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}
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define arm_aapcs_vfpcc <2 x i64> @signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: signbit_mask_v2i64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov r0, s3
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; CHECK-NEXT: vmov r1, s1
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; CHECK-NEXT: asrs r0, r0, #31
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; CHECK-NEXT: asrs r1, r1, #31
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; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
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; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
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; CHECK-NEXT: vand q0, q1, q0
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; CHECK-NEXT: bx lr
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%cond = icmp slt <2 x i64> %a, zeroinitializer
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%r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer
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ret <2 x i64> %r
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}
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