forked from OSchip/llvm-project
TableGen/GlobalISel: Fix constraining REG_SEQUENCE operands
This was hitting the default instruction constraint code which uses the register classes in the instruction def, which REG_SEQUENCE does not have. Fixes not constraining the register class for AMDGPU fneg/fabs patterns, which would fail when the use was another generic, unconstrained instruction. Another oddity I noticed is that the temporary registers are created with an unnecessary, but incorrect 16-bit LLT but this shouldn't matter. I'm also still unclear why root and sub-instructions have to be handled differently.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
229e392b4e
commit
cb5dc3765b
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@ -201,11 +201,11 @@ body: |
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; GCN-LABEL: name: fabs_s64_ss
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; GCN: [[FABS:%[0-9]+]]:sreg_64(s64) = G_FABS [[COPY]]
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; GCN: $sgpr0_sgpr1 = COPY [[FABS]](s64)
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; GCN: [[FABS:%[0-9]+]]:sgpr(s64) = G_FABS [[COPY]]
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; GCN: S_ENDPGM 0, implicit [[FABS]](s64)
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = G_FABS %0
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$sgpr0_sgpr1 = COPY %1
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S_ENDPGM 0, implicit %1
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...
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---
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@ -225,10 +225,10 @@ body: |
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; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
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; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]]
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = G_FABS %0
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$vgpr0_vgpr1 = COPY %1
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S_ENDPGM 0, implicit %1
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...
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---
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@ -243,9 +243,9 @@ body: |
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; GCN-LABEL: name: fabs_s64_vs
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; GCN: [[FABS:%[0-9]+]]:vreg_64(s64) = G_FABS [[COPY]]
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; GCN: $vgpr0_vgpr1 = COPY [[FABS]](s64)
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; GCN: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
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; GCN: S_ENDPGM 0, implicit [[FABS]](s64)
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s64) = G_FABS %0
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$vgpr0_vgpr1 = COPY %1
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S_ENDPGM 0, implicit %1
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...
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@ -206,10 +206,10 @@ body: |
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
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; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
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; GCN: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = G_FNEG %0
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$sgpr0_sgpr1 = COPY %1
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S_ENDPGM 0, implicit %1
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...
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---
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@ -229,10 +229,10 @@ body: |
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; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_XOR_B32_e32_]], %subreg.sub1
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; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]]
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = G_FNEG %0
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$vgpr0_vgpr1 = COPY %1
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S_ENDPGM 0, implicit %1
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...
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---
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@ -247,11 +247,12 @@ body: |
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; GCN-LABEL: name: fneg_s64_vs
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; GCN: [[FNEG:%[0-9]+]]:vreg_64(s64) = G_FNEG [[COPY]]
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; GCN: $vgpr0_vgpr1 = COPY [[FNEG]](s64)
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; GCN: [[FNEG:%[0-9]+]]:vgpr(s64) = G_FNEG [[COPY]]
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; GCN: S_ENDPGM 0, implicit [[FNEG]](s64)
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s64) = G_FNEG %0
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$vgpr0_vgpr1 = COPY %1
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S_ENDPGM 0, implicit %1
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...
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---
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@ -268,11 +269,11 @@ body: |
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
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; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: $sgpr0 = COPY [[S_OR_B32_]]
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; GCN: S_ENDPGM 0, implicit [[S_OR_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_FABS %0
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%2:sgpr(s32) = G_FNEG %1
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$sgpr0 = COPY %2
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S_ENDPGM 0, implicit %2
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...
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---
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@ -289,11 +290,11 @@ body: |
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
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; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]]
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; GCN: S_ENDPGM 0, implicit [[V_XOR_B32_e32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = G_FABS %0
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%2:vgpr(s32) = G_FNEG %0
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$vgpr0 = COPY %2
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S_ENDPGM 0, implicit %2
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...
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---
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@ -311,11 +312,11 @@ body: |
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; GCN: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147483648
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; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32(s32) = V_XOR_B32_e32 [[S_MOV_B32_]](s16), [[FABS]](s32), implicit $exec
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; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]](s32)
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; GCN: S_ENDPGM 0, implicit [[V_XOR_B32_e32_]](s32)
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = G_FABS %0
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%2:vgpr(s32) = G_FNEG %1
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$vgpr0 = COPY %2
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S_ENDPGM 0, implicit %2
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...
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---
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@ -472,11 +473,11 @@ body: |
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
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; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
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; GCN: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = G_FABS %0
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%2:sgpr(s64) = G_FNEG %1
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$sgpr0_sgpr1 = COPY %2
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S_ENDPGM 0, implicit %2
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...
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---
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@ -496,11 +497,11 @@ body: |
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; GCN: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_OR_B32_e32_]], %subreg.sub1
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; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]]
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = G_FABS %0
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%2:vgpr(s64) = G_FNEG %1
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$vgpr0_vgpr1 = COPY %2
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S_ENDPGM 0, implicit %2
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...
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---
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@ -521,9 +522,9 @@ body: |
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; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32(s16) = V_XOR_B32_e32 [[COPY1]](s32), [[V_MOV_B32_e32_]](s32), implicit $exec
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub0(s64)
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64(s64) = REG_SEQUENCE [[COPY2]](s32), %subreg.sub0, [[V_XOR_B32_e32_]](s16), %subreg.sub1
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; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]](s64)
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]](s64)
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s64) = G_FABS %0
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%2:vgpr(s64) = G_FNEG %1
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$vgpr0_vgpr1 = COPY %2
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S_ENDPGM 0, implicit %2
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...
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@ -56,7 +56,26 @@ def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
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// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DRegs*/1,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC SRegs*/0,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, /*RC SRegs*/0,
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def : Pat<(i32 (sext SOP:$src)),
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(REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0,
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(SUBSOME_INSN SOP:$src), sub1)>;
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// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ZEXT,
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// CHECK: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC DRegs*/1,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC SRegs*/0,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, /*RC SRegs*/0,
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SOME_INSN,
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// Make sure operands are constrained when REG_SEQUENCE isn't the root instruction.
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def : Pat<(i32 (zext SOP:$src)),
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(SOME_INSN (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0,
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(SUBSOME_INSN SOP:$src), sub1))>;
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@ -4281,6 +4281,29 @@ GlobalISelEmitter::createAndImportSubInstructionRenderer(
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return InsertPtOrError.get();
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}
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if (OpName == "REG_SEQUENCE") {
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auto SuperClass = inferRegClassFromPattern(Dst->getChild(0));
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M.insertAction<ConstrainOperandToRegClassAction>(
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InsertPt, DstMIBuilder.getInsnID(), 0, **SuperClass);
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unsigned Num = Dst->getNumChildren();
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for (unsigned I = 1; I != Num; I += 2) {
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TreePatternNode *SubRegChild = Dst->getChild(I + 1);
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auto SubIdx = inferSubRegIndexForNode(SubRegChild);
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if (!SubIdx)
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return failedImport("REG_SEQUENCE child is not a subreg index");
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const auto SrcRCDstRCPair =
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(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
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assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
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M.insertAction<ConstrainOperandToRegClassAction>(
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InsertPt, DstMIBuilder.getInsnID(), I, *SrcRCDstRCPair->second);
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}
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return InsertPtOrError.get();
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}
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M.insertAction<ConstrainOperandsToDefinitionAction>(InsertPt,
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DstMIBuilder.getInsnID());
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return InsertPtOrError.get();
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@ -4934,6 +4957,30 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
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return std::move(M);
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}
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if (DstIName == "REG_SEQUENCE") {
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auto SuperClass = inferRegClassFromPattern(Dst->getChild(0));
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M.addAction<ConstrainOperandToRegClassAction>(0, 0, **SuperClass);
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unsigned Num = Dst->getNumChildren();
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for (unsigned I = 1; I != Num; I += 2) {
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TreePatternNode *SubRegChild = Dst->getChild(I + 1);
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auto SubIdx = inferSubRegIndexForNode(SubRegChild);
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if (!SubIdx)
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return failedImport("REG_SEQUENCE child is not a subreg index");
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const auto SrcRCDstRCPair =
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(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
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M.addAction<ConstrainOperandToRegClassAction>(0, I,
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*SrcRCDstRCPair->second);
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}
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++NumPatternImported;
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return std::move(M);
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}
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M.addAction<ConstrainOperandsToDefinitionAction>(0);
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// We're done with this pattern! It's eligible for GISel emission; return it.
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