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[DAGCombiner] Add vector support to (mul (shl X, Y), Z) -> (shl (mul X, Z), Y) style combines 

llvm-svn: 284122
This commit is contained in:
Simon Pilgrim 2016-10-13 14:04:35 +00:00
parent ee3c7e0d42
commit cb59b5257c
2 changed files with 8 additions and 10 deletions
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13
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -2148,11 +2148,10 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
getShiftAmountTy(N0.getValueType()))));
}
APInt Val;
// (mul (shl X, c1), c2) -> (mul X, c2 << c1)
if (N1IsConst && N0.getOpcode() == ISD::SHL &&
(ISD::isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
isa<ConstantSDNode>(N0.getOperand(1)))) {
if (N0.getOpcode() == ISD::SHL &&
isConstantOrConstantVector(N1) &&
isConstantOrConstantVector(N0.getOperand(1))) {
SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
AddToWorklist(C3.getNode());
return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
@ -2162,14 +2161,14 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
// use.
{
SDValue Sh(nullptr, 0), Y(nullptr, 0);
// Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
if (N0.getOpcode() == ISD::SHL &&
(ISD::isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
isa<ConstantSDNode>(N0.getOperand(1))) &&
isConstantOrConstantVector(N0.getOperand(1)) &&
N0.getNode()->hasOneUse()) {
Sh = N0; Y = N1;
} else if (N1.getOpcode() == ISD::SHL &&
isa<ConstantSDNode>(N1.getOperand(1)) &&
isConstantOrConstantVector(N1.getOperand(1)) &&
N1.getNode()->hasOneUse()) {
Sh = N1; Y = N0;
}

5
llvm/test/CodeGen/X86/combine-mul.ll
View File

@ -146,7 +146,6 @@ define <4 x i32> @combine_vec_mul_shl_const(<4 x i32> %x) {
;
; AVX-LABEL: combine_vec_mul_shl_const:
; AVX: # BB#0:
; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
@ -164,8 +163,8 @@ define <4 x i32> @combine_vec_mul_shl_oneuse0(<4 x i32> %x, <4 x i32> %y) {
;
; AVX-LABEL: combine_vec_mul_shl_oneuse0:
; AVX: # BB#0:
; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
%2 = mul <4 x i32> %1, %y
@ -181,8 +180,8 @@ define <4 x i32> @combine_vec_mul_shl_oneuse1(<4 x i32> %x, <4 x i32> %y) {
;
; AVX-LABEL: combine_vec_mul_shl_oneuse1:
; AVX: # BB#0:
; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpmulld %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
%2 = mul <4 x i32> %y, %1