forked from OSchip/llvm-project
[DAGCombiner] reduce extract subvector of concat
If we are extracting a chunk of a vector that's a fraction of an operand of the concatenated vector operand, we can extract directly from one of those original operands. This is another suggestion from PR42024: https://bugs.llvm.org/show_bug.cgi?id=42024#c2 But I'm not sure yet if it will make any difference on those patterns. It seems to help a few existing AVX512 tests though. Differential Revision: https://reviews.llvm.org/D72361
This commit is contained in:
Sanjay Patel
parent
84ce46269c
commit
cb5612e2df
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@ -18594,8 +18594,22 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
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if (ConcatSrcNumElts == ExtNumElts)
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return V.getOperand(ConcatOpIdx);
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// TODO: Handle the case where the concat operands are larger than the
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// result of this extract by extracting directly from a concat op.
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// If the concatenated source vectors are a multiple length of this extract,
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// then extract a fraction of one of those source vectors directly from a
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// concat operand. Example:
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// v2i8 extract_subvec (v16i8 concat (v8i8 X), (v8i8 Y), 14 -->
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// v2i8 extract_subvec v8i8 Y, 6
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if (ConcatSrcNumElts % ExtNumElts == 0) {
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SDLoc DL(N);
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unsigned NewExtIdx = ExtIdx - ConcatOpIdx * ConcatSrcNumElts;
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assert(NewExtIdx + ExtNumElts <= ConcatSrcNumElts &&
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"Trying to extract from >1 concat operand?");
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assert(NewExtIdx % ExtNumElts == 0 &&
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"Extract index is not a multiple of the input vector length.");
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SDValue NewIndexC = DAG.getIntPtrConstant(NewExtIdx, DL);
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NVT,
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V.getOperand(ConcatOpIdx), NewIndexC);
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}
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}
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V = peekThroughBitcasts(V);
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@ -462,14 +462,12 @@ define void @avg_v48i8(<48 x i8>* %a, <48 x i8>* %b) nounwind {
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; AVX512BW-NEXT: vmovdqa (%rdi), %xmm0
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; AVX512BW-NEXT: vmovdqa 16(%rdi), %xmm1
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; AVX512BW-NEXT: vmovdqa 32(%rdi), %xmm2
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; AVX512BW-NEXT: vpavgb 16(%rsi), %xmm1, %xmm1
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; AVX512BW-NEXT: vpavgb 32(%rsi), %xmm2, %xmm2
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; AVX512BW-NEXT: vpavgb (%rsi), %xmm0, %xmm0
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; AVX512BW-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; AVX512BW-NEXT: vpavgb 32(%rsi), %xmm2, %xmm1
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; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm1
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; AVX512BW-NEXT: vmovdqu %ymm0, (%rax)
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; AVX512BW-NEXT: vextracti32x4 $2, %zmm1, (%rax)
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; AVX512BW-NEXT: vzeroupper
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; AVX512BW-NEXT: vpavgb 16(%rsi), %xmm1, %xmm1
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; AVX512BW-NEXT: vmovdqu %xmm1, (%rax)
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; AVX512BW-NEXT: vmovdqu %xmm0, (%rax)
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; AVX512BW-NEXT: vmovdqu %xmm2, (%rax)
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; AVX512BW-NEXT: retq
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%1 = load <48 x i8>, <48 x i8>* %a
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%2 = load <48 x i8>, <48 x i8>* %b
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@ -5,13 +5,12 @@ define <112 x i8> @pr34657(<112 x i8>* %src) local_unnamed_addr {
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; CHECK-LABEL: pr34657:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: vmovups 64(%rsi), %ymm0
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; CHECK-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1]
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; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm1
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; CHECK-NEXT: vmovups (%rsi), %zmm2
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; CHECK-NEXT: vmovaps %ymm0, 64(%rdi)
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; CHECK-NEXT: vmovaps %zmm2, (%rdi)
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; CHECK-NEXT: vextractf32x4 $2, %zmm1, 96(%rdi)
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; CHECK-NEXT: vmovups (%rsi), %zmm0
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; CHECK-NEXT: vmovups 64(%rsi), %ymm1
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; CHECK-NEXT: vmovups 96(%rsi), %xmm2
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; CHECK-NEXT: vmovaps %xmm2, 96(%rdi)
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; CHECK-NEXT: vmovaps %ymm1, 64(%rdi)
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; CHECK-NEXT: vmovaps %zmm0, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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@ -1055,64 +1055,24 @@ ret void
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}
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define void @interleaved_store_vf16_i8_stride3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <48 x i8>* %p) {
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; AVX1-LABEL: interleaved_store_vf16_i8_stride3:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
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; AVX1-NEXT: vpalignr {{.*#+}} xmm3 = xmm1[11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,10]
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; AVX1-NEXT: vpalignr {{.*#+}} xmm4 = xmm0[5,6,7,8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4]
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; AVX1-NEXT: vpalignr {{.*#+}} xmm0 = xmm3[5,6,7,8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4]
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; AVX1-NEXT: vpalignr {{.*#+}} xmm2 = xmm2[5,6,7,8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4]
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; AVX1-NEXT: vpalignr {{.*#+}} xmm1 = xmm4[5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4]
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5]
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; AVX1-NEXT: vpshufb %xmm3, %xmm1, %xmm1
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; AVX1-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[5,6,7,8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4]
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; AVX1-NEXT: vpshufb %xmm3, %xmm0, %xmm0
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; AVX1-NEXT: vpalignr {{.*#+}} xmm2 = xmm2[5,6,7,8,9,10,11,12,13,14,15],xmm4[0,1,2,3,4]
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; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2
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; AVX1-NEXT: vmovdqu %xmm0, 16(%rdi)
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; AVX1-NEXT: vmovdqu %xmm1, (%rdi)
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; AVX1-NEXT: vmovdqu %xmm2, 32(%rdi)
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: interleaved_store_vf16_i8_stride3:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
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; AVX2-NEXT: vpalignr {{.*#+}} xmm3 = xmm1[11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,10]
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; AVX2-NEXT: vpalignr {{.*#+}} xmm4 = xmm0[5,6,7,8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4]
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; AVX2-NEXT: vpalignr {{.*#+}} xmm0 = xmm3[5,6,7,8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4]
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; AVX2-NEXT: vpalignr {{.*#+}} xmm2 = xmm2[5,6,7,8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4]
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; AVX2-NEXT: vpalignr {{.*#+}} xmm1 = xmm4[5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4]
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; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5]
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; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
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; AVX2-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[5,6,7,8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4]
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; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
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; AVX2-NEXT: vpalignr {{.*#+}} xmm2 = xmm2[5,6,7,8,9,10,11,12,13,14,15],xmm4[0,1,2,3,4]
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; AVX2-NEXT: vpshufb %xmm3, %xmm2, %xmm2
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; AVX2-NEXT: vmovdqu %xmm0, 16(%rdi)
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; AVX2-NEXT: vmovdqu %xmm1, (%rdi)
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; AVX2-NEXT: vmovdqu %xmm2, 32(%rdi)
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: interleaved_store_vf16_i8_stride3:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
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; AVX512-NEXT: vpalignr {{.*#+}} xmm3 = xmm1[11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,10]
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; AVX512-NEXT: vpalignr {{.*#+}} xmm4 = xmm0[5,6,7,8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4]
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; AVX512-NEXT: vpalignr {{.*#+}} xmm0 = xmm3[5,6,7,8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4]
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; AVX512-NEXT: vpalignr {{.*#+}} xmm2 = xmm2[5,6,7,8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4]
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; AVX512-NEXT: vpalignr {{.*#+}} xmm1 = xmm4[5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4]
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; AVX512-NEXT: vmovdqa {{.*#+}} xmm3 = [0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5]
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; AVX512-NEXT: vpshufb %xmm3, %xmm1, %xmm1
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; AVX512-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[5,6,7,8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4]
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; AVX512-NEXT: vpshufb %xmm3, %xmm0, %xmm0
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; AVX512-NEXT: vpalignr {{.*#+}} xmm2 = xmm2[5,6,7,8,9,10,11,12,13,14,15],xmm4[0,1,2,3,4]
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; AVX512-NEXT: vpshufb %xmm3, %xmm2, %xmm2
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; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
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; AVX512-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm1
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; AVX512-NEXT: vmovdqu %ymm0, (%rdi)
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; AVX512-NEXT: vextracti32x4 $2, %zmm1, 32(%rdi)
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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; AVX-LABEL: interleaved_store_vf16_i8_stride3:
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; AVX: # %bb.0:
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; AVX-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5]
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; AVX-NEXT: vpalignr {{.*#+}} xmm3 = xmm1[11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,10]
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; AVX-NEXT: vpalignr {{.*#+}} xmm4 = xmm0[5,6,7,8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4]
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; AVX-NEXT: vpalignr {{.*#+}} xmm0 = xmm3[5,6,7,8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4]
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; AVX-NEXT: vpalignr {{.*#+}} xmm2 = xmm2[5,6,7,8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4]
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; AVX-NEXT: vpalignr {{.*#+}} xmm1 = xmm4[5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4]
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; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5]
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; AVX-NEXT: vpshufb %xmm3, %xmm1, %xmm1
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; AVX-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[5,6,7,8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4]
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; AVX-NEXT: vpshufb %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vpalignr {{.*#+}} xmm2 = xmm2[5,6,7,8,9,10,11,12,13,14,15],xmm4[0,1,2,3,4]
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; AVX-NEXT: vpshufb %xmm3, %xmm2, %xmm2
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; AVX-NEXT: vmovdqu %xmm0, 16(%rdi)
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; AVX-NEXT: vmovdqu %xmm1, (%rdi)
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; AVX-NEXT: vmovdqu %xmm2, 32(%rdi)
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; AVX-NEXT: retq
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%1 = shufflevector <16 x i8> %a, <16 x i8> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
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%2 = shufflevector <16 x i8> %c, <16 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%interleaved.vec = shufflevector <32 x i8> %1, <32 x i8> %2, <48 x i32> <i32 0, i32 16, i32 32, i32 1, i32 17, i32 33, i32 2, i32 18, i32 34, i32 3, i32 19, i32 35, i32 4, i32 20, i32 36, i32 5, i32 21, i32 37, i32 6, i32 22, i32 38, i32 7, i32 23, i32 39, i32 8, i32 24, i32 40, i32 9, i32 25, i32 41, i32 10, i32 26, i32 42, i32 11, i32 27, i32 43, i32 12, i32 28, i32 44, i32 13, i32 29, i32 45, i32 14, i32 30, i32 46, i32 15, i32 31, i32 47>
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