From cb2deb2aaf85d5df5d412c3f7b0b6c91e3d294bc Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Wed, 17 Feb 2010 22:42:54 +0000 Subject: [PATCH] Remove the NEON N2VSInt instruction class: it's only used in one place and since it has no pattern, there's not much point in distinguishing an "N2VS" class for intrinsics anyway. llvm-svn: 96525 --- llvm/lib/Target/ARM/ARMInstrNEON.td | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 6d7f242127c0..f981572c76c9 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -586,14 +586,7 @@ class N2VQ op24_23, bits<2> op21_20, bits<2> op19_18, (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src", "", [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>; -// Basic 2-register intrinsics: single-, double- and quad-register. -class N2VSInt op24_23, bits<2> op21_20, bits<2> op19_18, - bits<2> op17_16, bits<5> op11_7, bit op4, - InstrItinClass itin, string OpcodeStr, string Dt, - ValueType ResTy, ValueType OpTy, Intrinsic IntOp> - : N2V; +// Basic 2-register intrinsics, both double- and quad-register. class N2VDInt op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, @@ -3018,8 +3011,9 @@ def : N3VSPat; // Vector Absolute used for single-precision FP let neverHasSideEffects = 1 in -def VABSfd_sfp : N2VSInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, IIC_VUNAD, - "vabs", "f32", v2f32, v2f32, int_arm_neon_vabs>; +def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0, + (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD, + "vabs", "f32", "$dst, $src", "", []>; def : N2VSPat; // Vector Negate used for single-precision FP