forked from OSchip/llvm-project
[AArch64][GlobalISel] Select trn1 and trn2
Same idea as for zip, uzp, etc. Teach the post-legalizer combiner to recognize G_SHUFFLE_VECTORs that are trn1/trn2 instructions. - Add G_TRN1 and G_TRN2 - Port mask matching code from AArch64ISelLowering - Produce G_TRN1 and G_TRN2 in the post-legalizer combiner - Select via importer Add select-trn.mir to test selection. Add postlegalizer-combiner-trn.mir to test the combine. This is similar to the existing arm64-trn test. Note that both of these tests contain things we currently don't legalize. I figured it would be easier to test these now rather than later, since once we legalize the G_SHUFFLE_VECTORs, it's not guaranteed that someone will update the tests. Differential Revision: https://reviews.llvm.org/D81182
This commit is contained in:
Jessica Paquette
parent
de019b88dd
commit
cb2d8b30ad
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@ -56,9 +56,16 @@ def dup: GICombineRule <
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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def trn : GICombineRule<
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchTRN(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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// Combines which replace a G_SHUFFLE_VECTOR with a target-specific pseudo
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// instruction.
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def shuffle_vector_pseudos : GICombineGroup<[dup, rev, zip, uzp]>;
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def shuffle_vector_pseudos : GICombineGroup<[dup, rev, zip, uzp, trn]>;
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def AArch64PostLegalizerCombinerHelper
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: GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper",
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@ -80,6 +80,19 @@ def G_DUP: AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type1:$lane);
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}
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// Represents a trn1 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_TRN1 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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}
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// Represents a trn2 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_TRN2 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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}
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def : GINodeEquiv<G_REV16, AArch64rev16>;
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def : GINodeEquiv<G_REV32, AArch64rev32>;
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@ -89,3 +102,5 @@ def : GINodeEquiv<G_UZP2, AArch64uzp2>;
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def : GINodeEquiv<G_ZIP1, AArch64zip1>;
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def : GINodeEquiv<G_ZIP2, AArch64zip2>;
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def : GINodeEquiv<G_DUP, AArch64dup>;
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def : GINodeEquiv<G_TRN1, AArch64trn1>;
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def : GINodeEquiv<G_TRN2, AArch64trn2>;
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@ -95,6 +95,22 @@ static bool isREVMask(ArrayRef<int> M, unsigned EltSize, unsigned NumElts,
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return true;
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}
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/// Determines if \p M is a shuffle vector mask for a TRN of \p NumElts.
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/// Whether or not G_TRN1 or G_TRN2 should be used is stored in \p WhichResult.
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static bool isTRNMask(ArrayRef<int> M, unsigned NumElts,
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unsigned &WhichResult) {
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if (NumElts % 2 != 0)
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return false;
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WhichResult = (M[0] == 0 ? 0 : 1);
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for (unsigned i = 0; i < NumElts; i += 2) {
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if ((M[i] >= 0 && static_cast<unsigned>(M[i]) != i + WhichResult) ||
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(M[i + 1] >= 0 &&
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static_cast<unsigned>(M[i + 1]) != i + NumElts + WhichResult))
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return false;
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}
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return true;
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}
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/// Determines if \p M is a shuffle vector mask for a UZP of \p NumElts.
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/// Whether or not G_UZP1 or G_UZP2 should be used is stored in \p WhichResult.
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static bool isUZPMask(ArrayRef<int> M, unsigned NumElts,
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@ -158,6 +174,24 @@ static bool matchREV(MachineInstr &MI, MachineRegisterInfo &MRI,
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return false;
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}
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/// \return true if a G_SHUFFLE_VECTOR instruction \p MI can be replaced with
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/// a G_TRN1 or G_TRN2 instruction.
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static bool matchTRN(MachineInstr &MI, MachineRegisterInfo &MRI,
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ShuffleVectorPseudo &MatchInfo) {
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assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR);
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unsigned WhichResult;
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ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask();
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Register Dst = MI.getOperand(0).getReg();
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unsigned NumElts = MRI.getType(Dst).getNumElements();
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if (!isTRNMask(ShuffleMask, NumElts, WhichResult))
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return false;
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unsigned Opc = (WhichResult == 0) ? AArch64::G_TRN1 : AArch64::G_TRN2;
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Register V1 = MI.getOperand(1).getReg();
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Register V2 = MI.getOperand(2).getReg();
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MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
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return true;
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}
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/// \return true if a G_SHUFFLE_VECTOR instruction \p MI can be replaced with
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/// a G_UZP1 or G_UZP2 instruction.
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///
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@ -0,0 +1,234 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Check that we produce G_TRN1 or G_TRN2 when we have an appropriate shuffle
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# mask.
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#
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...
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---
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name: trn1_v8s8
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d0, $d1
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; CHECK-LABEL: name: trn1_v8s8
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
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; CHECK: [[TRN1_:%[0-9]+]]:_(<8 x s8>) = G_TRN1 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[TRN1_]](<8 x s8>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<8 x s8>) = COPY $d0
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%1:_(<8 x s8>) = COPY $d1
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%2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(0, 8, 2, 10, 4, 12, 6, 14)
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$d0 = COPY %2(<8 x s8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: trn2_v8s8
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d0, $d1
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; CHECK-LABEL: name: trn2_v8s8
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
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; CHECK: [[TRN2_:%[0-9]+]]:_(<8 x s8>) = G_TRN2 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[TRN2_]](<8 x s8>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<8 x s8>) = COPY $d0
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%1:_(<8 x s8>) = COPY $d1
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%2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(1, 9, 3, 11, 5, 13, 7, 15)
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$d0 = COPY %2(<8 x s8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: trn1_v16s8
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $q0, $q1
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; CHECK-LABEL: name: trn1_v16s8
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
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; CHECK: [[TRN1_:%[0-9]+]]:_(<16 x s8>) = G_TRN1 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[TRN1_]](<16 x s8>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<16 x s8>) = COPY $q0
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%1:_(<16 x s8>) = COPY $q1
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%2:_(<16 x s8>) = G_SHUFFLE_VECTOR %0(<16 x s8>), %1, shufflemask(0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30)
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$q0 = COPY %2(<16 x s8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: trn2_v16s8
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $q0, $q1
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; CHECK-LABEL: name: trn2_v16s8
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
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; CHECK: [[TRN2_:%[0-9]+]]:_(<16 x s8>) = G_TRN2 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[TRN2_]](<16 x s8>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<16 x s8>) = COPY $q0
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%1:_(<16 x s8>) = COPY $q1
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%2:_(<16 x s8>) = G_SHUFFLE_VECTOR %0(<16 x s8>), %1, shufflemask(1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31)
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$q0 = COPY %2(<16 x s8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: trn1_v4s32
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $q0, $q1
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; CHECK-LABEL: name: trn1_v4s32
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK: [[TRN1_:%[0-9]+]]:_(<4 x s32>) = G_TRN1 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[TRN1_]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = COPY $q1
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%2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 4, 2, 6)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: trn2_v4s32
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $q0, $q1
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; CHECK-LABEL: name: trn2_v4s32
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK: [[TRN2_:%[0-9]+]]:_(<4 x s32>) = G_TRN2 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[TRN2_]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = COPY $q1
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%2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(1, 5, 3, 7)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: redundant_with_zip1
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d0, $d1
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; 2 x s32 TRN is redundant with ZIP. Make sure we prioritize ZIP.
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;
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; CHECK-LABEL: name: redundant_with_zip1
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
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; CHECK: [[ZIP1_:%[0-9]+]]:_(<2 x s32>) = G_ZIP1 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[ZIP1_]](<2 x s32>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = COPY $d1
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%2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(0, 2)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: redundant_with_zip2
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d0, $d1
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; 2 x s32 TRN is redundant with ZIP. Make sure we prioritize ZIP.
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;
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; CHECK-LABEL: name: redundant_with_zip2
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
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; CHECK: [[ZIP2_:%[0-9]+]]:_(<2 x s32>) = G_ZIP2 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[ZIP2_]](<2 x s32>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = COPY $d1
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%2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 3)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: trn1_undef
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d0, $d1
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; Undef shuffle indices should not prevent matching to G_TRN1.
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;
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; CHECK-LABEL: name: trn1_undef
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
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; CHECK: [[TRN1_:%[0-9]+]]:_(<8 x s8>) = G_TRN1 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[TRN1_]](<8 x s8>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<8 x s8>) = COPY $d0
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%1:_(<8 x s8>) = COPY $d1
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%2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(0, 8, -1, -1, 4, 12, 6, 14)
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$d0 = COPY %2(<8 x s8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: trn2_undef
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d0, $d1
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; Undef shuffle indices should not prevent matching to G_TRN2.
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;
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; CHECK-LABEL: name: trn2_undef
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
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; CHECK: [[TRN2_:%[0-9]+]]:_(<8 x s8>) = G_TRN2 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[TRN2_]](<8 x s8>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<8 x s8>) = COPY $d0
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%1:_(<8 x s8>) = COPY $d1
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%2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(1, -1, 3, 11, 5, 13, -1, -1)
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$d0 = COPY %2(<8 x s8>)
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RET_ReallyLR implicit $d0
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@ -0,0 +1,300 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Test that we can select G_TRN1 and G_TRN2.
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#
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# Each testcase is named based off of the instruction which should be selected.
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...
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---
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name: TRN1v2i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: TRN1v2i32
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[TRN1v2i32_:%[0-9]+]]:fpr64 = TRN1v2i32 [[COPY]], [[COPY1]]
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; CHECK: RET_ReallyLR
|
||||
%0:fpr(<2 x s32>) = COPY $d0
|
||||
%1:fpr(<2 x s32>) = COPY $d1
|
||||
%2:fpr(<2 x s32>) = G_TRN1 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN1v2i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: TRN1v2i64
|
||||
; CHECK: liveins: $q0, $q1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
||||
; CHECK: [[TRN1v2i64_:%[0-9]+]]:fpr128 = TRN1v2i64 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<2 x s64>) = COPY $q0
|
||||
%1:fpr(<2 x s64>) = COPY $q1
|
||||
%2:fpr(<2 x s64>) = G_TRN1 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN1v4i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $d0, $d1
|
||||
; CHECK-LABEL: name: TRN1v4i16
|
||||
; CHECK: liveins: $d0, $d1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
||||
; CHECK: [[TRN1v4i16_:%[0-9]+]]:fpr64 = TRN1v4i16 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<4 x s16>) = COPY $d0
|
||||
%1:fpr(<4 x s16>) = COPY $d1
|
||||
%2:fpr(<4 x s16>) = G_TRN1 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN1v4i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: TRN1v4i32
|
||||
; CHECK: liveins: $q0, $q1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
||||
; CHECK: [[TRN1v4i32_:%[0-9]+]]:fpr128 = TRN1v4i32 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<4 x s32>) = COPY $q0
|
||||
%1:fpr(<4 x s32>) = COPY $q1
|
||||
%2:fpr(<4 x s32>) = G_TRN1 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN1v8i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $d0, $d1
|
||||
; CHECK-LABEL: name: TRN1v8i8
|
||||
; CHECK: liveins: $d0, $d1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
||||
; CHECK: [[TRN1v8i8_:%[0-9]+]]:fpr64 = TRN1v8i8 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<8 x s8>) = COPY $d0
|
||||
%1:fpr(<8 x s8>) = COPY $d1
|
||||
%2:fpr(<8 x s8>) = G_TRN1 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN1v8i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: TRN1v8i16
|
||||
; CHECK: liveins: $q0, $q1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
||||
; CHECK: [[TRN1v8i16_:%[0-9]+]]:fpr128 = TRN1v8i16 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<8 x s16>) = COPY $q0
|
||||
%1:fpr(<8 x s16>) = COPY $q1
|
||||
%2:fpr(<8 x s16>) = G_TRN1 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN1v16i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: TRN1v16i8
|
||||
; CHECK: liveins: $q0, $q1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
||||
; CHECK: [[TRN1v16i8_:%[0-9]+]]:fpr128 = TRN1v16i8 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<16 x s8>) = COPY $q0
|
||||
%1:fpr(<16 x s8>) = COPY $q1
|
||||
%2:fpr(<16 x s8>) = G_TRN1 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN2v2i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $d0, $d1
|
||||
; CHECK-LABEL: name: TRN2v2i32
|
||||
; CHECK: liveins: $d0, $d1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
||||
; CHECK: [[TRN2v2i32_:%[0-9]+]]:fpr64 = TRN2v2i32 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<2 x s32>) = COPY $d0
|
||||
%1:fpr(<2 x s32>) = COPY $d1
|
||||
%2:fpr(<2 x s32>) = G_TRN2 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN2v2i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: TRN2v2i64
|
||||
; CHECK: liveins: $q0, $q1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
||||
; CHECK: [[TRN2v2i64_:%[0-9]+]]:fpr128 = TRN2v2i64 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<2 x s64>) = COPY $q0
|
||||
%1:fpr(<2 x s64>) = COPY $q1
|
||||
%2:fpr(<2 x s64>) = G_TRN2 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN2v4i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $d0, $d1
|
||||
; CHECK-LABEL: name: TRN2v4i16
|
||||
; CHECK: liveins: $d0, $d1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
||||
; CHECK: [[TRN2v4i16_:%[0-9]+]]:fpr64 = TRN2v4i16 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<4 x s16>) = COPY $d0
|
||||
%1:fpr(<4 x s16>) = COPY $d1
|
||||
%2:fpr(<4 x s16>) = G_TRN2 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN2v4i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: TRN2v4i32
|
||||
; CHECK: liveins: $q0, $q1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
||||
; CHECK: [[TRN2v4i32_:%[0-9]+]]:fpr128 = TRN2v4i32 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<4 x s32>) = COPY $q0
|
||||
%1:fpr(<4 x s32>) = COPY $q1
|
||||
%2:fpr(<4 x s32>) = G_TRN2 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN2v8i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $d0, $d1
|
||||
; CHECK-LABEL: name: TRN2v8i8
|
||||
; CHECK: liveins: $d0, $d1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
||||
; CHECK: [[TRN2v8i8_:%[0-9]+]]:fpr64 = TRN2v8i8 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<8 x s8>) = COPY $d0
|
||||
%1:fpr(<8 x s8>) = COPY $d1
|
||||
%2:fpr(<8 x s8>) = G_TRN2 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN2v8i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: TRN2v8i16
|
||||
; CHECK: liveins: $q0, $q1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
||||
; CHECK: [[TRN2v8i16_:%[0-9]+]]:fpr128 = TRN2v8i16 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<8 x s16>) = COPY $q0
|
||||
%1:fpr(<8 x s16>) = COPY $q1
|
||||
%2:fpr(<8 x s16>) = G_TRN2 %0, %1
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
---
|
||||
name: TRN2v16i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: TRN2v16i8
|
||||
; CHECK: liveins: $q0, $q1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
||||
; CHECK: [[TRN2v16i8_:%[0-9]+]]:fpr128 = TRN2v16i8 [[COPY]], [[COPY1]]
|
||||
; CHECK: RET_ReallyLR
|
||||
%0:fpr(<16 x s8>) = COPY $q0
|
||||
%1:fpr(<16 x s8>) = COPY $q1
|
||||
%2:fpr(<16 x s8>) = G_TRN2 %0, %1
|
||||
RET_ReallyLR
|
||||
Loading…
Reference in New Issue