GlobalISel: Add known bits to InstructionSelector

AMDGPU uses this for some addressing mode selection patterns. The
analysis run itself doesn't do anything so it seems easier to just
always require this than adding a way to opt in.

llvm-svn: 370388
This commit is contained in:
Matt Arsenault 2019-08-29 17:24:32 +00:00
parent e1327e696e
commit caff0a88dd
5 changed files with 16 additions and 4 deletions

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@ -31,6 +31,7 @@ namespace llvm {
class APInt; class APInt;
class APFloat; class APFloat;
class GISelKnownBits;
class MachineInstr; class MachineInstr;
class MachineInstrBuilder; class MachineInstrBuilder;
class MachineFunction; class MachineFunction;
@ -381,11 +382,15 @@ public:
virtual bool select(MachineInstr &I) = 0; virtual bool select(MachineInstr &I) = 0;
CodeGenCoverage *CoverageInfo = nullptr; CodeGenCoverage *CoverageInfo = nullptr;
GISelKnownBits *KnownBits = nullptr;
MachineFunction *MF = nullptr; MachineFunction *MF = nullptr;
/// Setup per-MF selector state. /// Setup per-MF selector state.
virtual void setupMF(MachineFunction &mf, CodeGenCoverage &covinfo) { virtual void setupMF(MachineFunction &mf,
GISelKnownBits &KB,
CodeGenCoverage &covinfo) {
CoverageInfo = &covinfo; CoverageInfo = &covinfo;
KnownBits = &KB;
MF = &mf; MF = &mf;
} }

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@ -12,6 +12,7 @@
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h" #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/ADT/PostOrderIterator.h" #include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/Twine.h" #include "llvm/ADT/Twine.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h" #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/GlobalISel/Utils.h" #include "llvm/CodeGen/GlobalISel/Utils.h"
@ -53,6 +54,8 @@ InstructionSelect::InstructionSelect() : MachineFunctionPass(ID) { }
void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const { void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<TargetPassConfig>(); AU.addRequired<TargetPassConfig>();
AU.addRequired<GISelKnownBitsAnalysis>();
AU.addPreserved<GISelKnownBitsAnalysis>();
getSelectionDAGFallbackAnalysisUsage(AU); getSelectionDAGFallbackAnalysisUsage(AU);
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
@ -64,12 +67,13 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
return false; return false;
LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n'); LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
GISelKnownBits &KB = getAnalysis<GISelKnownBitsAnalysis>().get(MF);
const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>(); const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector(); InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
CodeGenCoverage CoverageInfo; CodeGenCoverage CoverageInfo;
assert(ISel && "Cannot work without InstructionSelector"); assert(ISel && "Cannot work without InstructionSelector");
ISel->setupMF(MF, CoverageInfo); ISel->setupMF(MF, KB, CoverageInfo);
// An optimization remark emitter. Used to report failures. // An optimization remark emitter. Used to report failures.
MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr); MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);

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@ -54,8 +54,9 @@ public:
bool select(MachineInstr &I) override; bool select(MachineInstr &I) override;
static const char *getName() { return DEBUG_TYPE; } static const char *getName() { return DEBUG_TYPE; }
void setupMF(MachineFunction &MF, CodeGenCoverage &CoverageInfo) override { void setupMF(MachineFunction &MF, GISelKnownBits &KB,
InstructionSelector::setupMF(MF, CoverageInfo); CodeGenCoverage &CoverageInfo) override {
InstructionSelector::setupMF(MF, KB, CoverageInfo);
// hasFnAttribute() is expensive to call on every BRCOND selection, so // hasFnAttribute() is expensive to call on every BRCOND selection, so
// cache it here for each run of the selector. // cache it here for each run of the selector.

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@ -53,6 +53,7 @@
; VERIFY-NEXT: Verify generated machine code ; VERIFY-NEXT: Verify generated machine code
; ENABLED-O0-NEXT: Localizer ; ENABLED-O0-NEXT: Localizer
; VERIFY-O0-NEXT: Verify generated machine code ; VERIFY-O0-NEXT: Verify generated machine code
; ENABLED-NEXT: Analysis for ComputingKnownBits
; ENABLED-NEXT: InstructionSelect ; ENABLED-NEXT: InstructionSelect
; VERIFY-NEXT: Verify generated machine code ; VERIFY-NEXT: Verify generated machine code
; ENABLED-NEXT: ResetMachineFunction ; ENABLED-NEXT: ResetMachineFunction

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@ -41,6 +41,7 @@
; CHECK-NEXT: Legalizer ; CHECK-NEXT: Legalizer
; CHECK-NEXT: RegBankSelect ; CHECK-NEXT: RegBankSelect
; CHECK-NEXT: Localizer ; CHECK-NEXT: Localizer
; CHECK-NEXT: Analysis for ComputingKnownBits
; CHECK-NEXT: InstructionSelect ; CHECK-NEXT: InstructionSelect
; CHECK-NEXT: ResetMachineFunction ; CHECK-NEXT: ResetMachineFunction
; CHECK-NEXT: AArch64 Instruction Selection ; CHECK-NEXT: AArch64 Instruction Selection