forked from OSchip/llvm-project
[ARM] Promote fp16 frem
Promote fp16 frem operations on ARM to floats so they call fmodf. Differential Revision: https://reviews.llvm.org/D62321 llvm-svn: 361713
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@ -1142,6 +1142,11 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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}
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}
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}
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}
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// FP16 often need to be promoted to call lib functions
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if (Subtarget->hasFullFP16()) {
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setOperationAction(ISD::FREM, MVT::f16, Promote);
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}
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if (Subtarget->hasNEON()) {
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if (Subtarget->hasNEON()) {
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// vmin and vmax aren't available in a scalar form, so we use
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// vmin and vmax aren't available in a scalar form, so we use
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// a NEON instruction with an undef lane instead.
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// a NEON instruction with an undef lane instead.
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@ -57,14 +57,25 @@ define void @test_fdiv(half* %p, half* %q) {
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ret void
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ret void
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}
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}
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; FIXME
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define arm_aapcs_vfpcc void @test_frem(half* %p, half* %q) {
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;define void @test_frem(half* %p, half* %q) {
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; CHECK-LABEL: test_frem:
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; %a = load half, half* %p, align 2
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; CHECK: .save {r4, lr}
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; %b = load half, half* %q, align 2
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; CHECK-NEXT: push {r4, lr}
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; %r = frem half %a, %b
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; CHECK-NEXT: vldr.16 s2, [r1]
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; store half %r, half* %p
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; CHECK-NEXT: vldr.16 s0, [r0]
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; ret void
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; CHECK-NEXT: mov r4, r0
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;}
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; CHECK-NEXT: vcvtb.f32.f16 s0, s0
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; CHECK-NEXT: vcvtb.f32.f16 s1, s2
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; CHECK-NEXT: bl fmodf
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vstr.16 s0, [r4]
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; CHECK-NEXT: pop {r4, pc}
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%a = load half, half* %p, align 2
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%b = load half, half* %q, align 2
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%r = frem half %a, %b
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store half %r, half* %p
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ret void
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}
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define void @test_load_store(half* %p, half* %q) {
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define void @test_load_store(half* %p, half* %q) {
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; CHECK-LABEL: test_load_store:
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; CHECK-LABEL: test_load_store:
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