forked from OSchip/llvm-project
[GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELT
This adds instruction selection support for G_EXTRACT_VECTOR_ELT for cases where the index is defined by a G_CONSTANT. It also factos out the lane copy opcode selection part into its own function, `getLaneCopyOpcode`. This is used by both `selectUnmergeValues` and `selectExtractElt`. Differential Revision: https://reviews.llvm.org/D58469 llvm-svn: 355344
This commit is contained in:
Jessica Paquette
parent
4737abc71c
commit
caf62b1d47
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@ -78,6 +78,7 @@ private:
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void collectShuffleMaskIndices(MachineInstr &I, MachineRegisterInfo &MRI,
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SmallVectorImpl<int> &Idxs) const;
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bool selectShuffleVector(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool selectExtractElt(MachineInstr &I, MachineRegisterInfo &MRI) const;
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unsigned emitConstantPoolEntry(Constant *CPVal, MachineFunction &MF) const;
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MachineInstr *emitLoadFromConstantPool(Constant *CPVal,
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@ -1709,6 +1710,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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return selectUnmergeValues(I, MRI);
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case TargetOpcode::G_SHUFFLE_VECTOR:
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return selectShuffleVector(I, MRI);
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case TargetOpcode::G_EXTRACT_VECTOR_ELT:
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return selectExtractElt(I, MRI);
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}
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return false;
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@ -1787,6 +1790,127 @@ bool AArch64InstructionSelector::selectMergeValues(
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return true;
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}
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static bool getLaneCopyOpcode(unsigned &CopyOpc, unsigned &ExtractSubReg,
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const unsigned EltSize) {
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// Choose a lane copy opcode and subregister based off of the size of the
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// vector's elements.
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switch (EltSize) {
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case 16:
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CopyOpc = AArch64::CPYi16;
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ExtractSubReg = AArch64::hsub;
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break;
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case 32:
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CopyOpc = AArch64::CPYi32;
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ExtractSubReg = AArch64::ssub;
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break;
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case 64:
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CopyOpc = AArch64::CPYi64;
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ExtractSubReg = AArch64::dsub;
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break;
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default:
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// Unknown size, bail out.
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LLVM_DEBUG(dbgs() << "Elt size '" << EltSize << "' unsupported.\n");
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return false;
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}
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return true;
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}
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bool AArch64InstructionSelector::selectExtractElt(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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assert(I.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT &&
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"unexpected opcode!");
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unsigned DstReg = I.getOperand(0).getReg();
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const LLT NarrowTy = MRI.getType(DstReg);
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const unsigned SrcReg = I.getOperand(1).getReg();
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const LLT WideTy = MRI.getType(SrcReg);
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assert(WideTy.getSizeInBits() >= NarrowTy.getSizeInBits() &&
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"source register size too small!");
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assert(NarrowTy.isScalar() && "cannot extract vector into vector!");
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// Need the lane index to determine the correct copy opcode.
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MachineOperand &LaneIdxOp = I.getOperand(2);
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assert(LaneIdxOp.isReg() && "Lane index operand was not a register?");
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if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) {
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LLVM_DEBUG(dbgs() << "Cannot extract into GPR.\n");
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return false;
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}
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// Find the instruction that defines the constant to extract from. There could
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// be any number of copies between the instruction and the definition of the
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// index. Skip them.
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MachineInstr *LaneDefInst = nullptr;
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for (LaneDefInst = MRI.getVRegDef(LaneIdxOp.getReg());
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LaneDefInst && LaneDefInst->isCopy();
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LaneDefInst = MRI.getVRegDef(LaneDefInst->getOperand(1).getReg())) {
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}
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// Did we find a def in the first place? If not, bail.
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if (!LaneDefInst) {
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LLVM_DEBUG(dbgs() << "Did not find VReg definition for " << LaneIdxOp
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<< "\n");
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return false;
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}
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// TODO: Handle extracts that don't use G_CONSTANT.
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if (LaneDefInst->getOpcode() != TargetOpcode::G_CONSTANT) {
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LLVM_DEBUG(dbgs() << "VRegs defined by anything other than G_CONSTANT "
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"currently unsupported.\n");
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return false;
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}
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unsigned LaneIdx = LaneDefInst->getOperand(1).getCImm()->getLimitedValue();
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unsigned CopyOpc = 0;
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unsigned ExtractSubReg = 0;
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if (!getLaneCopyOpcode(CopyOpc, ExtractSubReg, NarrowTy.getSizeInBits())) {
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LLVM_DEBUG(
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dbgs() << "Couldn't determine lane copy opcode for instruction.\n");
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return false;
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}
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const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
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const TargetRegisterClass *DstRC =
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getRegClassForTypeOnBank(NarrowTy, DstRB, RBI, true);
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if (!DstRC) {
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LLVM_DEBUG(dbgs() << "Could not determine destination register class.\n");
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return false;
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}
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const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
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const TargetRegisterClass *SrcRC =
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getRegClassForTypeOnBank(WideTy, SrcRB, RBI, true);
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if (!SrcRC) {
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LLVM_DEBUG(dbgs() << "Could not determine source register class.\n");
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return false;
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}
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// The register that we're going to copy into.
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unsigned InsertReg = SrcReg;
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MachineIRBuilder MIRBuilder(I);
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// Lane copies require 128-bit wide registers. If we're dealing with an
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// unpacked vector, then we need to move up to that width. Insert an implicit
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// def and a subregister insert to get us there.
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if (WideTy.getSizeInBits() != 128) {
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MachineInstr *ScalarToVector = emitScalarToVector(
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WideTy.getSizeInBits(), &AArch64::FPR128RegClass, SrcReg, MIRBuilder);
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if (!ScalarToVector)
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return false;
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InsertReg = ScalarToVector->getOperand(0).getReg();
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}
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MachineInstr *LaneCopyMI =
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MIRBuilder.buildInstr(CopyOpc, {DstReg}, {InsertReg}).addImm(LaneIdx);
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constrainSelectedInstRegOperands(*LaneCopyMI, TII, TRI, RBI);
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// Make sure that we actually constrain the initial copy.
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RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
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I.eraseFromParent();
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return true;
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}
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bool AArch64InstructionSelector::selectUnmergeValues(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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assert(I.getOpcode() == TargetOpcode::G_UNMERGE_VALUES &&
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@ -1823,24 +1947,8 @@ bool AArch64InstructionSelector::selectUnmergeValues(
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// vector's elements.
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unsigned CopyOpc = 0;
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unsigned ExtractSubReg = 0;
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switch (NarrowTy.getSizeInBits()) {
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case 16:
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CopyOpc = AArch64::CPYi16;
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ExtractSubReg = AArch64::hsub;
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break;
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case 32:
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CopyOpc = AArch64::CPYi32;
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ExtractSubReg = AArch64::ssub;
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break;
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case 64:
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CopyOpc = AArch64::CPYi64;
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ExtractSubReg = AArch64::dsub;
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break;
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default:
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// Unknown size, bail out.
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LLVM_DEBUG(dbgs() << "NarrowTy had unsupported size.\n");
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if (!getLaneCopyOpcode(CopyOpc, ExtractSubReg, NarrowTy.getSizeInBits()))
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return false;
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}
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// Set up for the lane copies.
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MachineBasicBlock &MBB = *I.getParent();
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@ -441,7 +441,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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.minScalar(2, s64)
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.legalIf([=](const LegalityQuery &Query) {
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const LLT &VecTy = Query.Types[1];
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return VecTy == v4s32 || VecTy == v2s64;
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return VecTy == v2s16 || VecTy == v4s16 || VecTy == v4s32 ||
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VecTy == v2s64 || VecTy == v2s32;
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});
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getActionDefinitionsBuilder(G_BUILD_VECTOR)
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@ -689,6 +689,14 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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}
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break;
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}
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case TargetOpcode::G_EXTRACT_VECTOR_ELT:
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// Destination and source need to be FPRs.
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OpRegBankIdx[0] = PMI_FirstFPR;
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OpRegBankIdx[1] = PMI_FirstFPR;
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// Index needs to be a GPR.
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OpRegBankIdx[2] = PMI_FirstGPR;
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break;
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case TargetOpcode::G_BUILD_VECTOR:
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// If the first source operand belongs to a FPR register bank, then make
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@ -0,0 +1,103 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s
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name: v2s32_fpr
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1.entry:
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liveins: $d0
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%0:_(<2 x s32>) = COPY $d0
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%2:_(s64) = G_CONSTANT i64 1
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%1:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %2(s64)
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: v4s32_gpr
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1.entry:
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liveins: $q0
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; CHECK-LABEL: name: v4s32_gpr
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0
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; CHECK: [[EVEC:%[0-9]+]]:fpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s64)
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; CHECK: $s0 = COPY [[EVEC]](s32)
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; CHECK: RET_ReallyLR implicit $s0
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%0:_(<4 x s32>) = COPY $q0
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%2:_(s64) = G_CONSTANT i64 0
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%1:_(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %2(s64)
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: v2s64_fpr
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1.entry:
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liveins: $q0
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; CHECK-LABEL: name: v2s64_fpr
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 2
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; CHECK: [[EVEC:%[0-9]+]]:fpr(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](s64)
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; CHECK: $d0 = COPY [[EVEC]](s64)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<2 x s64>) = COPY $q0
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%2:_(s64) = G_CONSTANT i64 2
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%1:_(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %2(s64)
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$d0 = COPY %1(s64)
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RET_ReallyLR implicit $d0
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...
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---
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name: v4s16_fpr
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1.entry:
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liveins: $d0
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; CHECK-LABEL: name: v4s16_fpr
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s16>) = COPY $d0
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; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1
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; CHECK: [[EVEC:%[0-9]+]]:fpr(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s16>), [[C]](s64)
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; CHECK: $h0 = COPY [[EVEC]](s16)
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; CHECK: RET_ReallyLR implicit $h0
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%0:_(<4 x s16>) = COPY $d0
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%2:_(s64) = G_CONSTANT i64 1
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%1:_(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %2(s64)
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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@ -0,0 +1,94 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select %s -o - | FileCheck %s
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...
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---
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name: v2s32_fpr
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: gpr }
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- { id: 3, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: v2s32_fpr
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK: [[CPYi32_:%[0-9]+]]:fpr32 = CPYi32 [[INSERT_SUBREG]], 1
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; CHECK: $s0 = COPY [[CPYi32_]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(<2 x s32>) = COPY $d0
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%2:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: v2s64_fpr
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: gpr }
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- { id: 3, class: fpr }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v2s64_fpr
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 2
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; CHECK: $d0 = COPY [[CPYi64_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s64>) = COPY $q0
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%2:gpr(s64) = G_CONSTANT i64 2
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %3(s64)
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$d0 = COPY %1(s64)
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RET_ReallyLR implicit $d0
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...
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---
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name: v4s16_fpr
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: gpr }
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- { id: 3, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: v4s16_fpr
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1
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; CHECK: $h0 = COPY [[CPYi16_]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:fpr(<4 x s16>) = COPY $d0
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%2:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %3(s64)
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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