forked from OSchip/llvm-project
Fix a bug in i32->f64 conversion lowering
llvm-svn: 25211
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@ -622,9 +622,9 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
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case ISD::SINT_TO_FP: {
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assert(Op.getOperand(0).getValueType() == MVT::i32);
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Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
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SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
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// Convert the int value to FP in an FP register.
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return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op);
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return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
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}
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case ISD::BR_CC: {
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SDOperand Chain = Op.getOperand(0);
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