forked from OSchip/llvm-project
parent
d14247a9e5
commit
cab9a2eef5
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@ -379,6 +379,7 @@ public:
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/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
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/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
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SDValue getNOT(SDValue Val, MVT VT);
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SDValue getNOT(SDValue Val, MVT VT);
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SDValue getNOT(DebugLoc DL, SDValue Val, MVT VT);
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/// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
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/// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
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/// a flag result (to ensure it's not CSE'd).
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/// a flag result (to ensure it's not CSE'd).
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@ -846,6 +846,23 @@ SDValue SelectionDAG::getNOT(SDValue Val, MVT VT) {
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return getNode(ISD::XOR, VT, Val, NegOne);
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return getNode(ISD::XOR, VT, Val, NegOne);
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}
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}
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/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
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///
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SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) {
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SDValue NegOne;
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if (VT.isVector()) {
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MVT EltVT = VT.getVectorElementType();
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SDValue NegOneElt = getConstant(EltVT.getIntegerVTBitMask(), EltVT);
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std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt);
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NegOne = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), VT,
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&NegOnes[0], NegOnes.size());
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} else {
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NegOne = getConstant(VT.getIntegerVTBitMask(), VT);
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}
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return getNode(ISD::XOR, DL, VT, Val, NegOne);
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}
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SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
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SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
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MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
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MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
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assert((EltVT.getSizeInBits() >= 64 ||
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assert((EltVT.getSizeInBits() >= 64 ||
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