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GlobalISel: Fix narrowing of (G_ASHR i64:x, 32) 

Reviewers: arsenm

Subscribers: jvesely, wdng, nhaehnle, rovka, hiraditya, volkan, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74950
This commit is contained in:
Jay Foad 2020-02-20 20:21:30 +00:00
parent 6a479220b5
commit cab39e4b8c
2 changed files with 4 additions and 4 deletions
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4
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
View File

@ -1449,8 +1449,8 @@ bool CombinerHelper::applyCombineShiftToUnmerge(MachineInstr &MI,
if (ShiftVal == HalfSize) { if (ShiftVal == HalfSize) {
// (G_ASHR i64:x, 32) -> // (G_ASHR i64:x, 32) ->
// G_MERGE_VALUES lo_32(x), (G_ASHR hi_32(x), 31) // G_MERGE_VALUES hi_32(x), (G_ASHR hi_32(x), 31)
Builder.buildMerge(DstReg, { Unmerge.getReg(0), Hi }); Builder.buildMerge(DstReg, { Unmerge.getReg(1), Hi });
} else if (ShiftVal == Size - 1) { } else if (ShiftVal == Size - 1) {
// Don't need a second shift. // Don't need a second shift.
// (G_ASHR i64:x, 63) -> // (G_ASHR i64:x, 63) ->

4
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
View File

@ -14,7 +14,7 @@ body: |
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[ASHR]](s32) ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[ASHR]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_CONSTANT i64 32 %1:_(s64) = G_CONSTANT i64 32
@ -35,7 +35,7 @@ body: |
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[ASHR]](s32) ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[ASHR]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 32 %1:_(s32) = G_CONSTANT i32 32