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ARM parsing and encoding for LDRBT instruction. 

Fix the instruction representation to correctly only allow post-indexed form.
Add tests.

llvm-svn: 137074
This commit is contained in:
Jim Grosbach 2011-08-08 23:28:47 +00:00
parent 03ac20fc66
commit cab35c0836
2 changed files with 44 additions and 11 deletions
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39
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -2034,20 +2034,37 @@ def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
let Inst{11-0} = addr{11-0};
let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
}
def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
(ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
"ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
// {17-14} Rn
// {13} 1 == Rm, 0 == imm12
def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$addr, am2offset_reg:$offset),
IndexModePost, LdFrm, IIC_iLoad_bh_ru,
"ldrbt", "\t$Rt, $addr, $offset",
"$addr.base = $Rn_wb", []> {
// {12} isAdd
// {11-0} imm12/Rm
bits<18> addr;
let Inst{25} = addr{13};
let Inst{23} = addr{12};
bits<14> offset;
bits<4> addr;
let Inst{25} = 1;
let Inst{23} = offset{12};
let Inst{21} = 1; // overwrite
let Inst{19-16} = addr{17-14};
let Inst{11-0} = addr{11-0};
let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
let Inst{19-16} = addr;
let Inst{11-0} = offset{11-0};
}
def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$addr, am2offset_imm:$offset),
IndexModePost, LdFrm, IIC_iLoad_bh_ru,
"ldrbt", "\t$Rt, $addr, $offset",
"$addr.base = $Rn_wb", []> {
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
let Inst{25} = 0;
let Inst{23} = offset{12};
let Inst{21} = 1; // overwrite
let Inst{19-16} = addr;
let Inst{11-0} = offset{11-0};
}
multiclass AI3ldrT<bits<4> op, string opc> {

16
llvm/test/MC/ARM/arm-memory-instructions.s
View File

@ -89,3 +89,19 @@ _func:
@ CHECK: ldr r8, [r4], -r5 @ encoding: [0x05,0x80,0x14,0xe6]
@ CHECK: ldr r7, [r12, -r1, lsl #15] @ encoding: [0x81,0x77,0x1c,0xe7]
@ CHECK: ldr r5, [r2], r9, asr #15 @ encoding: [0xc9,0x57,0x92,0xe6]
@------------------------------------------------------------------------------
@ LDRBT
@------------------------------------------------------------------------------
@ FIXME: Optional offset operand.
ldrbt r3, [r1], #4
ldrbt r2, [r8], #-8
ldrbt r8, [r7], r6
ldrbt r1, [r2], -r6, lsl #12
@ CHECK: ldrbt r3, [r1], #4 @ encoding: [0x04,0x30,0xf1,0xe4]
@ CHECK: ldrbt r2, [r8], #-8 @ encoding: [0x08,0x20,0x78,0xe4]
@ CHECK: ldrbt r8, [r7], r6 @ encoding: [0x06,0x80,0xf7,0xe6]
@ CHECK: ldrbt r1, [r2], -r6, lsl #12 @ encoding: [0x06,0x16,0x72,0xe6]