forked from OSchip/llvm-project
AArch64: fix even more JIT failures
The last patch corrected some issues, but constant-pool entries had actual codegen bugs in the large memory model (which MCJIT uses). llvm-svn: 187126
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@ -259,15 +259,15 @@ AArch64DAGToDAGISel::getConstantPoolItemAddress(SDLoc DL,
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LitAddr = CurDAG->getMachineNode(
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AArch64::MOVZxii, DL, PtrVT,
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CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0, AArch64II::MO_ABS_G3),
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CurDAG->getTargetConstant(0, MVT::i32));
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CurDAG->getTargetConstant(3, MVT::i32));
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LitAddr = CurDAG->getMachineNode(
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AArch64::MOVKxii, DL, PtrVT, SDValue(LitAddr, 0),
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CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0, AArch64II::MO_ABS_G2_NC),
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CurDAG->getTargetConstant(0, MVT::i32));
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CurDAG->getTargetConstant(2, MVT::i32));
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LitAddr = CurDAG->getMachineNode(
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AArch64::MOVKxii, DL, PtrVT, SDValue(LitAddr, 0),
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CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0, AArch64II::MO_ABS_G1_NC),
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CurDAG->getTargetConstant(0, MVT::i32));
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CurDAG->getTargetConstant(1, MVT::i32));
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LitAddr = CurDAG->getMachineNode(
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AArch64::MOVKxii, DL, PtrVT, SDValue(LitAddr, 0),
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CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0, AArch64II::MO_ABS_G0_NC),
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@ -2048,7 +2048,7 @@ AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
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AArch64II::MO_TPREL_G0_NC);
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TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
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DAG.getTargetConstant(0, MVT::i32)), 0);
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DAG.getTargetConstant(1, MVT::i32)), 0);
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TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
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TPOff, LoVar,
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DAG.getTargetConstant(0, MVT::i32)), 0);
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