diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index ac8f568da189..ba71dc05a8fc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -417,11 +417,15 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
     }
   }
 
-  if (VCCUsed)
+  if (VCCUsed || FlatUsed)
     MaxSGPR += 2;
 
-  if (FlatUsed)
+  if (FlatUsed) {
     MaxSGPR += 2;
+    // 2 additional for VI+.
+    if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
+      MaxSGPR += 2;
+  }
 
   // We found the maximum register index. They start at 0, so add one to get the
   // number of registers.
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
new file mode 100644
index 000000000000..e2ae3353ae1d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=amdgcn -mcpu=kaveri -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=CI
+; RUN: llc < %s -march=amdgcn -mcpu=fiji -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=VI
+
+; GCN-LABEL: {{^}}no_vcc_no_flat:
+; GCN: ; NumSgprs: 8
+define void @no_vcc_no_flat() {
+entry:
+  call void asm sideeffect "", "~{SGPR7}"()
+  ret void
+}
+
+; GCN-LABEL: {{^}}vcc_no_flat:
+; GCN: ; NumSgprs: 10
+define void @vcc_no_flat() {
+entry:
+  call void asm sideeffect "", "~{SGPR7},~{VCC}"()
+  ret void
+}
+
+; GCN-LABEL: {{^}}no_vcc_flat:
+; CI: ; NumSgprs: 12
+; VI: ; NumSgprs: 14
+define void @no_vcc_flat() {
+entry:
+  call void asm sideeffect "", "~{SGPR7},~{FLAT_SCR}"()
+  ret void
+}
+
+; GCN-LABEL: {{^}}vcc_flat:
+; CI: ; NumSgprs: 12
+; VI: ; NumSgprs: 14
+define void @vcc_flat() {
+entry:
+  call void asm sideeffect "", "~{SGPR7},~{VCC},~{FLAT_SCR}"()
+  ret void
+}