[X86] Autogenerate complete checks. NFC

llvm-svn: 357543

llvm/test/CodeGen/X86/dagcombine-shifts.ll

@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s
 
 ; fold (shl (zext (lshr (A, X))), X) -> (zext (shl (lshr (A, X)), X))
@@ -10,6 +11,12 @@
 ; and if there is only one use of the zext.
 
 define i16 @fun1(i8 zeroext %v) {
+; CHECK-LABEL: fun1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    andl $-16, %eax
+; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT:    retq
 entry:
   %shr = lshr i8 %v, 4
   %ext = zext i8 %shr to i16
@@ -17,13 +24,12 @@ entry:
   ret i16 %shl
 }
 
-; CHECK-LABEL: @fun1
-; CHECK: and
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: ret
-
 define i32 @fun2(i8 zeroext %v) {
+; CHECK-LABEL: fun2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    andl $-16, %eax
+; CHECK-NEXT:    retq
 entry:
   %shr = lshr i8 %v, 4
   %ext = zext i8 %shr to i32
@@ -31,13 +37,12 @@ entry:
   ret i32 %shl
 }
 
-; CHECK-LABEL: @fun2
-; CHECK: and
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: ret
-
 define i32 @fun3(i16 zeroext %v) {
+; CHECK-LABEL: fun3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    andl $-16, %eax
+; CHECK-NEXT:    retq
 entry:
   %shr = lshr i16 %v, 4
   %ext = zext i16 %shr to i32
@@ -45,13 +50,12 @@ entry:
   ret i32 %shl
 }
 
-; CHECK-LABEL: @fun3
-; CHECK: and
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: ret
-
 define i64 @fun4(i8 zeroext %v) {
+; CHECK-LABEL: fun4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    andl $-16, %eax
+; CHECK-NEXT:    retq
 entry:
   %shr = lshr i8 %v, 4
   %ext = zext i8 %shr to i64
@@ -59,13 +63,12 @@ entry:
   ret i64 %shl
 }
 
-; CHECK-LABEL: @fun4
-; CHECK: and
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: ret
-
 define i64 @fun5(i16 zeroext %v) {
+; CHECK-LABEL: fun5:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    andl $-16, %eax
+; CHECK-NEXT:    retq
 entry:
   %shr = lshr i16 %v, 4
   %ext = zext i16 %shr to i64
@@ -73,13 +76,12 @@ entry:
   ret i64 %shl
 }
 
-; CHECK-LABEL: @fun5
-; CHECK: and
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: ret
-
 define i64 @fun6(i32 zeroext %v) {
+; CHECK-LABEL: fun6:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    andl $-16, %eax
+; CHECK-NEXT:    retq
 entry:
   %shr = lshr i32 %v, 4
   %ext = zext i32 %shr to i64
@@ -87,15 +89,15 @@ entry:
   ret i64 %shl
 }
 
-; CHECK-LABEL: @fun6
-; CHECK: and
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: ret
-
 ; Don't fold the pattern if we use arithmetic shifts.
 
 define i64 @fun7(i8 zeroext %v) {
+; CHECK-LABEL: fun7:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sarb $4, %dil
+; CHECK-NEXT:    movzbl %dil, %eax
+; CHECK-NEXT:    shlq $4, %rax
+; CHECK-NEXT:    retq
 entry:
   %shr = ashr i8 %v, 4
   %ext = zext i8 %shr to i64
@@ -103,12 +105,13 @@ entry:
   ret i64 %shl
 }
 
-; CHECK-LABEL: @fun7
-; CHECK: sar
-; CHECK: shl
-; CHECK: ret
-
 define i64 @fun8(i16 zeroext %v) {
+; CHECK-LABEL: fun8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sarw $4, %di
+; CHECK-NEXT:    movzwl %di, %eax
+; CHECK-NEXT:    shlq $4, %rax
+; CHECK-NEXT:    retq
 entry:
   %shr = ashr i16 %v, 4
   %ext = zext i16 %shr to i64
@@ -116,12 +119,13 @@ entry:
   ret i64 %shl
 }
 
-; CHECK-LABEL: @fun8
-; CHECK: sar
-; CHECK: shl
-; CHECK: ret
-
 define i64 @fun9(i32 zeroext %v) {
+; CHECK-LABEL: fun9:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    sarl $4, %eax
+; CHECK-NEXT:    shlq $4, %rax
+; CHECK-NEXT:    retq
 entry:
   %shr = ashr i32 %v, 4
   %ext = zext i32 %shr to i64
@@ -129,15 +133,18 @@ entry:
   ret i64 %shl
 }
 
-; CHECK-LABEL: @fun9
-; CHECK: sar
-; CHECK: shl
-; CHECK: ret
-
 ; Don't fold the pattern if there is more than one use of the
 ; operand in input to the shift left.
 
 define i64 @fun10(i8 zeroext %v) {
+; CHECK-LABEL: fun10:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    shrb $4, %dil
+; CHECK-NEXT:    movzbl %dil, %ecx
+; CHECK-NEXT:    movq %rcx, %rax
+; CHECK-NEXT:    shlq $4, %rax
+; CHECK-NEXT:    orq %rcx, %rax
+; CHECK-NEXT:    retq
 entry:
   %shr = lshr i8 %v, 4
   %ext = zext i8 %shr to i64
@@ -146,12 +153,15 @@ entry:
   ret i64 %add
 }
 
-; CHECK-LABEL: @fun10
-; CHECK: shr
-; CHECK: shl
-; CHECK: ret
-
 define i64 @fun11(i16 zeroext %v) {
+; CHECK-LABEL: fun11:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    shrl $4, %edi
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    shlq $4, %rax
+; CHECK-NEXT:    leaq (%rax,%rdi), %rax
+; CHECK-NEXT:    retq
 entry:
   %shr = lshr i16 %v, 4
   %ext = zext i16 %shr to i64
@@ -160,12 +170,15 @@ entry:
   ret i64 %add
 }
 
-; CHECK-LABEL: @fun11
-; CHECK: shr
-; CHECK: shl
-; CHECK: ret
-
 define i64 @fun12(i32 zeroext %v) {
+; CHECK-LABEL: fun12:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    shrl $4, %edi
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    shlq $4, %rax
+; CHECK-NEXT:    leaq (%rax,%rdi), %rax
+; CHECK-NEXT:    retq
 entry:
   %shr = lshr i32 %v, 4
   %ext = zext i32 %shr to i64
@@ -174,23 +187,23 @@ entry:
   ret i64 %add
 }
 
-; CHECK-LABEL: @fun12
-; CHECK: shr
-; CHECK: shl
-; CHECK: ret
-
 ; PR17380
 ; Make sure that the combined dags are legal if we run the DAGCombiner after
-; Legalization took place. The add instruction is redundant and increases by 
+; Legalization took place. The add instruction is redundant and increases by
 ; one the number of uses of the zext. This prevents the transformation from
 ; firing before dags are legalized and optimized.
 ; Once the add is removed, the number of uses becomes one and therefore the
 ; dags are canonicalized. After Legalization, we need to make sure that the
 ; valuetype for the shift count is legal.
-; Verify also that we correctly fold the shl-shr sequence into an 
+; Verify also that we correctly fold the shl-shr sequence into an
 ; AND with bitmask.
 
 define void @g(i32 %a) {
+; CHECK-LABEL: g:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    andl $-4, %edi
+; CHECK-NEXT:    jmp f # TAILCALL
   %b = lshr i32 %a, 2
   %c = zext i32 %b to i64
   %d = add i64 %c, 1
@@ -199,11 +212,5 @@ define void @g(i32 %a) {
   ret void
 }
 
-; CHECK-LABEL: @g
-; CHECK-NOT: shr
-; CHECK-NOT: shl
-; CHECK: and
-; CHECK-NEXT: jmp
-
 declare void @f(i64)