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[PowerPC] Implement the isSelectSupported() target hook 

Summary:
PowerPC has scalar selects (isel) and vector mask selects (xxsel). But PowerPC
does not have vector CR selects, PowerPC does not support scalar condition 
selects on vectors.
In addition to implementing this hook, isSelectSupported() should return false
when the SelectSupportKind is ScalarCondVectorVal, so that predictable selects
are converted into branch sequences.

Reviewed By: steven.zhang,  hfinkel

Differential Revision: https://reviews.llvm.org/D55754

llvm-svn: 349727
This commit is contained in:
Kang Zhang 2018-12-20 06:19:59 +00:00
parent bd788ce5db
commit ca8db48974
2 changed files with 13 additions and 12 deletions
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5
llvm/lib/Target/PowerPC/PPCISelLowering.h
View File

@ -576,6 +576,11 @@ namespace llvm {
/// DAG node.
const char *getTargetNodeName(unsigned Opcode) const override;
bool isSelectSupported(SelectSupportKind Kind) const override {
// PowerPC does not support scalar condition selects on vectors.
return (Kind != SelectSupportKind::ScalarCondVectorVal);
}
/// getPreferredVectorAction - The code we generate when vector types are
/// legalized by promoting the integer element type is often much worse
/// than code we generate if we widen the type for applicable vector types.

20
llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
View File

@ -928,10 +928,8 @@ entry:
; CHECK-LABEL: @testv4floateq
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: bc 12, [[REG1]], .LBB[[BB1:[0-9_]+]]
; CHECK: vmr 3, 2
; CHECK: .LBB[[BB1]]
; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: bclr 12, [[REG1]], 0
; CHECK: vmr 2, 3
; CHECK: blr
}
@ -1065,7 +1063,7 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: bc 4, 2, .LBB[[BB]]
; CHECK: bclr 12, 2, 0
; CHECK: .LBB[[BB]]:
; CHECK: vmr 2, 3
; CHECK: blr
@ -1083,7 +1081,7 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: bc 12, 2, .LBB[[BB]]
; CHECK: bclr 4, 2, 0
; CHECK: .LBB[[BB]]:
; CHECK: vmr 2, 3
; CHECK: blr
@ -1134,10 +1132,8 @@ entry:
; CHECK-LABEL: @testv2doubleeq
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: bc 12, [[REG1]], .LBB[[BB55:[0-9_]+]]
; CHECK: vmr 3, 2
; CHECK: .LBB[[BB55]]
; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: bclr 12, [[REG1]], 0
; CHECK: vmr 2, 3
; CHECK: blr
}
@ -1188,7 +1184,7 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: bc 12, 2, .LBB[[BB]]
; CHECK: bclr 4, 2, 0
; CHECK: .LBB[[BB]]
; CHECK: vmr 2, 3
; CHECK: blr
@ -1206,7 +1202,7 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: bc 4, 2, .LBB[[BB]]
; CHECK: bclr 12, 2, 0
; CHECK: .LBB[[BB]]
; CHECK: vmr 2, 3
; CHECK: blr