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[DAGCombiner] fix miscompile in translating (X & undef) to shuffle 

See PR42982 for more context:
https://bugs.llvm.org/show_bug.cgi?id=42982
This commit is contained in:
Sanjay Patel 2020-01-03 14:57:35 -05:00
parent 7cdc60c3db
commit ca7fdd41bd
2 changed files with 5 additions and 3 deletions
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4
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -19769,8 +19769,10 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
int EltIdx = i / Split;
int SubIdx = i % Split;
SDValue Elt = RHS.getOperand(EltIdx);
// X & undef --> 0 (not undef). So this lane must be converted to choose
// from the zero constant vector (same as if the element had all 0-bits).
if (Elt.isUndef()) {
Indices.push_back(-1);
Indices.push_back(i + NumSubElts);
continue;
}

4
llvm/test/CodeGen/X86/combine-and.ll
View File

@ -163,13 +163,13 @@ define <4 x i32> @test14(<4 x i32> %A) {
ret <4 x i32> %1
}
; FIXME: X & undef must fold to 0. So lane 0 must choose from the zero vector.
; X & undef must fold to 0. So lane 0 must choose from the zero vector.
define <4 x i32> @undef_lane(<4 x i32> %x) {
; CHECK-LABEL: undef_lane:
; CHECK: # %bb.0:
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
; CHECK-NEXT: retq
%r = and <4 x i32> %x, <i32 undef, i32 4294967295, i32 0, i32 4294967295>
ret <4 x i32> %r