forked from OSchip/llvm-project
[NFC][CSKY] Resort the instruction description in td
Resort the instruction description in td to make it easy to upstream more instructions and add predicts later.
This commit is contained in:
Zi Xuan Wu
parent
95934c3a37
commit
ca31b43ae8
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@ -151,73 +151,88 @@ class UnOpFrag<dag res> : PatFrag<(ops node:$Src), res>;
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// Basic ALU instructions.
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// Basic ALU instructions.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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def ADDI32 : I_12<0x0, "addi32", add, oimm12>;
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def ADDI32 : I_12<0x0, "addi32", add, oimm12>;
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def SUBI32 : I_12<0x1, "subi32", sub, oimm12>;
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def SUBI32 : I_12<0x1, "subi32", sub, oimm12>;
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def ANDI32 : I_12<0x2, "andi32", and, uimm12>;
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def ORI32 : I_16_ZX<"ori32", uimm16,
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def ANDNI32 : I_12<0x3, "andni32", and, nimm12>;
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def ORI32 : I_16_ZX<"ori32", uimm16,
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[(set GPR:$rz, (or GPR:$rx, uimm16:$imm16))]>;
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[(set GPR:$rz, (or GPR:$rx, uimm16:$imm16))]>;
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def XORI32 : I_12<0x4, "xori32", xor, uimm12>;
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def XORI32 : I_12<0x4, "xori32", xor, uimm12>;
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def LSLI32 : I_5_XZ<0x12, 0x1, "lsli32",
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def ANDI32 : I_12<0x2, "andi32", and, uimm12>;
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(outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
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def ANDNI32 : I_12<0x3, "andni32", and, nimm12>;
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[(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
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def LSLI32 : I_5_XZ<0x12, 0x1, "lsli32",
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def LSRI32 : I_5_XZ<0x12, 0x2, "lsri32",
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(outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
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(outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
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[(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
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[(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
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def LSRI32 : I_5_XZ<0x12, 0x2, "lsri32",
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def ASRI32 : I_5_XZ<0x12, 0x4, "asri32",
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(outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
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(outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
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[(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
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[(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
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def ASRI32 : I_5_XZ<0x12, 0x4, "asri32",
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def ROTLI32 : I_5_XZ<0x12, 0x8, "rotli32",
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(outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
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(outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
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[(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
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[(set GPR:$rz, (rotl GPR:$rx, uimm5:$imm5))]>;
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def ROTLI32 : I_5_XZ<0x12, 0x8, "rotli32",
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(outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
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def ADDU32 : R_YXZ_SP_F1<0x0, 0x1,
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[(set GPR:$rz, (rotl GPR:$rx, uimm5:$imm5))]>;
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BinOpFrag<(add node:$LHS, node:$RHS)>, "addu32", 1>;
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def SUBU32 : R_YXZ_SP_F1<0x0, 0x4,
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BinOpFrag<(sub node:$LHS, node:$RHS)>, "subu32">;
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def AND32 : R_YXZ_SP_F1<0x8, 0x1,
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BinOpFrag<(and node:$LHS, node:$RHS)>, "and32", 1>;
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def ANDN32 : R_YXZ_SP_F1<0x8, 0x2,
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BinOpFrag<(and node:$LHS, (not node:$RHS))>, "andn32">;
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def OR32: R_YXZ_SP_F1<0x9, 0x1,
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BinOpFrag<(or node:$LHS, node:$RHS)>, "or32", 1>;
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def XOR32 : R_YXZ_SP_F1<0x9, 0x2,
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BinOpFrag<(xor node:$LHS, node:$RHS)>, "xor32", 1>;
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def NOR32 : R_YXZ_SP_F1<0x9, 0x4,
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BinOpFrag<(not (or node:$LHS, node:$RHS))>, "nor32", 1>;
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def LSL32 : R_YXZ_SP_F1<0x10, 0x1,
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BinOpFrag<(shl node:$LHS, node:$RHS)>, "lsl32">;
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def LSR32 : R_YXZ_SP_F1<0x10, 0x2,
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BinOpFrag<(srl node:$LHS, node:$RHS)>, "lsr32">;
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def ASR32 : R_YXZ_SP_F1<0x10, 0x4,
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BinOpFrag<(sra node:$LHS, node:$RHS)>, "asr32">;
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def MULT32 : R_YXZ_SP_F1<0x21, 0x1,
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BinOpFrag<(mul node:$LHS, node:$RHS)>, "mult32", 1>;
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def DIVS32 : R_YXZ_SP_F1<0x20, 0x2,
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BinOpFrag<(sdiv node:$LHS, node:$RHS)>, "divs32">;
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def DIVU32 : R_YXZ_SP_F1<0x20, 0x1,
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BinOpFrag<(udiv node:$LHS, node:$RHS)>, "divu32">;
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def IXH32 : R_YXZ_SP_F1<0x2, 0x1,
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BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 1)))>, "ixh32">;
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def IXW32 : R_YXZ_SP_F1<0x2, 0x2,
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BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 2)))>, "ixw32">;
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def IXD32 : R_YXZ_SP_F1<0x2, 0x4,
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BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 3)))>, "ixd32">;
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def NOT32 : R_XXZ<0b001001, 0b00100, (outs GPR:$rz), (ins GPR:$rx),
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"not32", [(set GPR:$rz, (not GPR:$rx))]>;
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def SEXT : I_5_XZ_U<0x16, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "sext32",
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[]>;
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def ZEXT : I_5_XZ_U<0x15, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "zext32",
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[]>;
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let isCommutable = 1 in
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def ADDU32 : R_YXZ_SP_F1<0x0, 0x1,
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BinOpFrag<(add node:$LHS, node:$RHS)>, "addu32", 1>;
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def SUBU32 : R_YXZ_SP_F1<0x0, 0x4,
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BinOpFrag<(sub node:$LHS, node:$RHS)>, "subu32">;
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def MULT32 : R_YXZ_SP_F1<0x21, 0x1,
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BinOpFrag<(mul node:$LHS, node:$RHS)>, "mult32", 1>;
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def AND32 : R_YXZ_SP_F1<0x8, 0x1,
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BinOpFrag<(and node:$LHS, node:$RHS)>, "and32", 1>;
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def ANDN32 : R_YXZ_SP_F1<0x8, 0x2,
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BinOpFrag<(and node:$LHS, (not node:$RHS))>, "andn32">;
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def OR32: R_YXZ_SP_F1<0x9, 0x1,
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BinOpFrag<(or node:$LHS, node:$RHS)>, "or32", 1>;
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def XOR32 : R_YXZ_SP_F1<0x9, 0x2,
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BinOpFrag<(xor node:$LHS, node:$RHS)>, "xor32", 1>;
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def NOR32 : R_YXZ_SP_F1<0x9, 0x4,
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BinOpFrag<(not (or node:$LHS, node:$RHS))>, "nor32", 1>;
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def NOT32 : R_XXZ<0b001001, 0b00100, (outs GPR:$rz), (ins GPR:$rx),
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"not32", [(set GPR:$rz, (not GPR:$rx))]>;
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def LSL32 : R_YXZ_SP_F1<0x10, 0x1,
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BinOpFrag<(shl node:$LHS, node:$RHS)>, "lsl32">;
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def LSR32 : R_YXZ_SP_F1<0x10, 0x2,
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BinOpFrag<(srl node:$LHS, node:$RHS)>, "lsr32">;
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def ASR32 : R_YXZ_SP_F1<0x10, 0x4,
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BinOpFrag<(sra node:$LHS, node:$RHS)>, "asr32">;
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def ROTL32 : R_YXZ_SP_F1<0x10, 0x8,
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BinOpFrag<(rotl node:$LHS, (and node:$RHS, 0x1f))>, "rotl32">;
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// TODO: Shift series instr. with carry.
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def IXH32 : R_YXZ_SP_F1<0x2, 0x1,
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BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 1)))>, "ixh32">;
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def IXW32 : R_YXZ_SP_F1<0x2, 0x2,
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BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 2)))>, "ixw32">;
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def IXD32 : R_YXZ_SP_F1<0x2, 0x4,
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BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 3)))>, "ixd32">;
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let isCommutable = 1 in
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def ADDC32 : R_YXZ<0x31, 0x0, 0x2, (outs GPR:$rz, CARRY:$cout),
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def ADDC32 : R_YXZ<0x31, 0x0, 0x2, (outs GPR:$rz, CARRY:$cout),
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(ins GPR:$rx, GPR:$ry, CARRY:$cin), "addc32", []>;
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(ins GPR:$rx, GPR:$ry, CARRY:$cin), "addc32", []>;
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def SUBC32 : R_YXZ<0x31, 0x0, 0x8, (outs GPR:$rz, CARRY:$cout),
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def SUBC32 : R_YXZ<0x31, 0x0, 0x8, (outs GPR:$rz, CARRY:$cout),
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(ins GPR:$rx, GPR:$ry, CARRY:$cin), "subc32", []>;
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(ins GPR:$rx, GPR:$ry, CARRY:$cin), "subc32", []>;
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// TODO: incf32.
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def DIVS32 : R_YXZ_SP_F1<0x20, 0x2,
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BinOpFrag<(sdiv node:$LHS, node:$RHS)>, "divs32">;
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def DIVU32 : R_YXZ_SP_F1<0x20, 0x1,
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BinOpFrag<(udiv node:$LHS, node:$RHS)>, "divu32">;
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def DECGT32 : I_5_XZ<0x4, 0x1, "decgt32",
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(outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
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def DECLT32 : I_5_XZ<0x4, 0x2, "declt32",
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(outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
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def DECNE32 : I_5_XZ<0x4, 0x4, "decne32",
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(outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
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// TODO: s/zext.
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def ZEXT32 : I_5_XZ_U<0x15, (outs GPR:$rz),
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(ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "zext32",[]>;
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def SEXT32 : I_5_XZ_U<0x16, (outs GPR:$rz),
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(ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "sext32", []>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Load & Store instructions.
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// Load & Store instructions.
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@ -226,46 +241,63 @@ def SUBC32 : R_YXZ<0x31, 0x0, 0x8, (outs GPR:$rz, CARRY:$cout),
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def LD32B : I_LD<AddrMode32B, 0x0, "ld32.b", uimm12>;
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def LD32B : I_LD<AddrMode32B, 0x0, "ld32.b", uimm12>;
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def LD32H : I_LD<AddrMode32H, 0x1, "ld32.h", uimm12_1>;
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def LD32H : I_LD<AddrMode32H, 0x1, "ld32.h", uimm12_1>;
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def LD32W : I_LD<AddrMode32WD, 0x2, "ld32.w", uimm12_2>;
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def LD32W : I_LD<AddrMode32WD, 0x2, "ld32.w", uimm12_2>;
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def LD32BS : I_LD<AddrMode32B, 0x4, "ld32.bs", uimm12>;
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def LD32HS : I_LD<AddrMode32H, 0x5, "ld32.hs", uimm12_1>;
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def LDR32B : I_LDR<0x0, "ldr32.b">;
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def LDR32BS : I_LDR<0x4, "ldr32.bs">;
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def LD32BS : I_LD<AddrMode32B, 0x4, "ld32.bs", uimm12>;
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def LDR32H : I_LDR<0x1, "ldr32.h">;
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def LD32HS : I_LD<AddrMode32H, 0x5, "ld32.hs", uimm12_1>;
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def LDR32HS : I_LDR<0x5, "ldr32.hs">;
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def LDR32W : I_LDR<0x2, "ldr32.w">;
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// TODO: LDM and STM.
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def ST32B : I_ST<AddrMode32B, 0x0, "st32.b", uimm12>;
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def ST32B : I_ST<AddrMode32B, 0x0, "st32.b", uimm12>;
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def ST32H : I_ST<AddrMode32H, 0x1, "st32.h", uimm12_1>;
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def ST32H : I_ST<AddrMode32H, 0x1, "st32.h", uimm12_1>;
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def ST32W : I_ST<AddrMode32WD, 0x2, "st32.w", uimm12_2>;
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def ST32W : I_ST<AddrMode32WD, 0x2, "st32.w", uimm12_2>;
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def STR32B : I_STR<0x0, "str32.b">;
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def STR32H : I_STR<0x1, "str32.h">;
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def LDR32B : I_LDR<0x0, "ldr32.b">;
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def STR32W : I_STR<0x2, "str32.w">;
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def LDR32BS : I_LDR<0x4, "ldr32.bs">;
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def LDR32H : I_LDR<0x1, "ldr32.h">;
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def LDR32HS : I_LDR<0x5, "ldr32.hs">;
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def LDR32W : I_LDR<0x2, "ldr32.w">;
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def STR32B : I_STR<0x0, "str32.b">;
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def STR32H : I_STR<0x1, "str32.h">;
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def STR32W : I_STR<0x2, "str32.w">;
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//TODO: SPILL_CARRY and RESTORE_CARRY.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Compare instructions.
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// Compare instructions.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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def CMPNEI32 : I_16_X<0x1A, "cmpnei32", uimm16>;
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def CMPNEI32 : I_16_X<0x1A, "cmpnei32", uimm16>;
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def CMPHSI32 : I_16_X<0x18, "cmphsi32", oimm16>;
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def CMPHSI32 : I_16_X<0x18, "cmphsi32", oimm16>;
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def CMPLTI32 : I_16_X<0x19, "cmplti32", oimm16>;
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def CMPLTI32 : I_16_X<0x19, "cmplti32", oimm16>;
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def CMPNE32 : R_YX<0x1, 0x4, "cmpne32">;
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def CMPHS32 : R_YX<0x1, 0x1, "cmphs32">;
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def CMPLT32 : R_YX<0x1, 0x2, "cmplt32">;
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def CMPNE32 : R_YX<0x1, 0x4, "cmpne32">;
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def CMPHS32 : R_YX<0x1, 0x1, "cmphs32">;
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def CMPLT32 : R_YX<0x1, 0x2, "cmplt32">;
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// TODO: setc and clrc.
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// TODO: test32 and tstnbz.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Data move instructions.
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// Data move instructions.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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def MOVT32 : R_ZX<0x3, 0x2, "movt32", []>;
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def MOVT32 : R_ZX<0x3, 0x2, "movt32", []>;
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def MOVF32 : R_ZX<0x3, 0x1, "movf32", []>;
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def MOVF32 : R_ZX<0x3, 0x1, "movf32", []>;
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def MOV32 : R_XZ<0x12, 0x1, "mov32">;
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def MOVI32 : I_16_MOV<0x10, "movi32", uimm16>;
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def MOVI32 : I_16_MOV<0x10, "movi32", uimm16>;
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def MOVIH32 : I_16_MOV<0x11, "movih32", uimm16_16_xform>;
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def MOVIH32 : I_16_MOV<0x11, "movih32", uimm16_16_xform>;
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def MVC32 : R_Z_1<0x1, 0x8, "mvc32">;
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def MOV32 : R_XZ<0x12, 0x1, "mov32">;
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def MVC32 : R_Z_1<0x1, 0x8, "mvc32">;
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// TODO: ISEL Pseudo.
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def MVCV32 : R_Z_1<0x1, 0x10, "mvcv32">;
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def MVCV32 : R_Z_1<0x1, 0x10, "mvcv32">;
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// TODO: clrf and clrt.
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def CLRF32 : R_Z_2<0xB, 0x1, "clrf32", []>;
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def CLRT32 : R_Z_2<0xB, 0x2, "clrt32", []>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Branch and call instructions.
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// Branch and call instructions.
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@ -283,25 +315,25 @@ let isBranch = 1, isTerminator = 1 in {
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}
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}
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def BEZ32 : I_16_X_L<0x8, "bez32", br_symbol>;
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def BEZ32 : I_16_X_L<0x8, "bez32", br_symbol>;
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def BNEZ32 : I_16_X_L<0x9, "bnez32", br_symbol>;
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def BNEZ32 : I_16_X_L<0x9, "bnez32", br_symbol>;
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def BHZ32 : I_16_X_L<0xA, "bhz32", br_symbol>;
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def BHZ32 : I_16_X_L<0xA, "bhz32", br_symbol>;
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def BLSZ32 : I_16_X_L<0xB, "blsz32", br_symbol>;
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def BLSZ32 : I_16_X_L<0xB, "blsz32", br_symbol>;
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def BLZ32 : I_16_X_L<0xC, "blz32", br_symbol>;
|
def BLZ32 : I_16_X_L<0xC, "blz32", br_symbol>;
|
||||||
def BHSZ32 : I_16_X_L<0xD, "bhsz32", br_symbol>;
|
def BHSZ32 : I_16_X_L<0xD, "bhsz32", br_symbol>;
|
||||||
|
|
||||||
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
|
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
|
||||||
def JMP32 : I_16_JX<0x6, "jmp32", [(brind GPR:$rx)]>; // jmp to register
|
def JMP32 : I_16_JX<0x6, "jmp32", [(brind GPR:$rx)]>; // jmp to register
|
||||||
def JMPI32 : I_16_L<0x16, (outs), (ins constpool_symbol:$imm16),
|
def JMPI32 : I_16_L<0x16, (outs), (ins constpool_symbol:$imm16),
|
||||||
"jmpi32\t$imm16", []>;
|
"jmpi32\t$imm16", []>;
|
||||||
}
|
}
|
||||||
|
|
||||||
let isCall = 1, Defs = [ R15 ] in
|
let isCall = 1, Defs = [ R15 ] in
|
||||||
def JSR32 : I_16_JX<0x7, "jsr32", []>;
|
def JSR32 : I_16_JX<0x7, "jsr32", []>;
|
||||||
|
|
||||||
let isCall = 1, Defs = [ R15 ] , mayLoad = 1 in
|
let isCall = 1, Defs = [ R15 ] , mayLoad = 1 in
|
||||||
def JSRI32: I_16_L<0x17, (outs),
|
def JSRI32: I_16_L<0x17, (outs),
|
||||||
(ins constpool_symbol:$imm16), "jsri32\t$imm16", []>;
|
(ins constpool_symbol:$imm16), "jsri32\t$imm16", []>;
|
||||||
|
|
||||||
|
|
||||||
def BSR32 : J<0x38, (outs), (ins call_symbol:$offset), "bsr32", []>;
|
def BSR32 : J<0x38, (outs), (ins call_symbol:$offset), "bsr32", []>;
|
||||||
|
|
@ -315,7 +347,8 @@ def BSR32_BR : J<0x38, (outs), (ins call_symbol:$offset), "bsr32", []>{
|
||||||
let Defs = [ R15 ];
|
let Defs = [ R15 ];
|
||||||
}
|
}
|
||||||
|
|
||||||
def RTS32 : I_16_RET<0x6, 0xF, "rts32", [(CSKY_RET)]>;
|
|
||||||
|
def RTS32 : I_16_RET<0x6, 0xF, "rts32", [(CSKY_RET)]>;
|
||||||
|
|
||||||
|
|
||||||
def RTE32 : I_16_RET_I<0, 0, "rte32", []>;
|
def RTE32 : I_16_RET_I<0, 0, "rte32", []>;
|
||||||
|
|
@ -330,5 +363,11 @@ def GRS32 : I_18_Z_L<0x3, "grs32\t$rz, $offset",
|
||||||
let mayLoad = 1, mayStore = 0 in {
|
let mayLoad = 1, mayStore = 0 in {
|
||||||
def LRW32 : I_16_Z_L<0x14, "lrw32", (ins constpool_symbol:$imm16), []>;
|
def LRW32 : I_16_Z_L<0x14, "lrw32", (ins constpool_symbol:$imm16), []>;
|
||||||
let isCodeGenOnly = 1 in
|
let isCodeGenOnly = 1 in
|
||||||
def LRW32_Gen : I_16_Z_L<0x14, "lrw32", (ins bare_symbol:$src1, constpool_symbol:$imm16), []>;
|
def LRW32_Gen : I_16_Z_L<0x14, "lrw32",
|
||||||
}
|
(ins bare_symbol:$src1, constpool_symbol:$imm16), []>;
|
||||||
|
}
|
||||||
|
|
||||||
|
// TODO: Atomic and fence instructions.
|
||||||
|
// TODO: Other operations.
|
||||||
|
// TODO: Special instructions.
|
||||||
|
// TODO: Pseudo for assembly.
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue