forked from OSchip/llvm-project
Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.
llvm-svn: 149216
This commit is contained in:
Craig Topper
parent
372dd1ea18
commit
ca29bcfc10
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@ -9213,7 +9213,7 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
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unsigned Opc = 0;
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ISD::CondCode CC = ISD::SETCC_INVALID;
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switch (IntNo) {
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default: break;
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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case Intrinsic::x86_sse_comieq_ss:
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case Intrinsic::x86_sse2_comieq_sd:
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Opc = X86ISD::COMI;
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@ -9285,6 +9285,196 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
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DAG.getConstant(X86CC, MVT::i8), Cond);
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return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
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}
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// XOP comparison intrinsics
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case Intrinsic::x86_xop_vpcomltb:
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case Intrinsic::x86_xop_vpcomltw:
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case Intrinsic::x86_xop_vpcomltd:
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case Intrinsic::x86_xop_vpcomltq:
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case Intrinsic::x86_xop_vpcomltub:
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case Intrinsic::x86_xop_vpcomltuw:
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case Intrinsic::x86_xop_vpcomltud:
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case Intrinsic::x86_xop_vpcomltuq:
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case Intrinsic::x86_xop_vpcomleb:
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case Intrinsic::x86_xop_vpcomlew:
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case Intrinsic::x86_xop_vpcomled:
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case Intrinsic::x86_xop_vpcomleq:
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case Intrinsic::x86_xop_vpcomleub:
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case Intrinsic::x86_xop_vpcomleuw:
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case Intrinsic::x86_xop_vpcomleud:
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case Intrinsic::x86_xop_vpcomleuq:
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case Intrinsic::x86_xop_vpcomgtb:
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case Intrinsic::x86_xop_vpcomgtw:
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case Intrinsic::x86_xop_vpcomgtd:
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case Intrinsic::x86_xop_vpcomgtq:
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case Intrinsic::x86_xop_vpcomgtub:
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case Intrinsic::x86_xop_vpcomgtuw:
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case Intrinsic::x86_xop_vpcomgtud:
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case Intrinsic::x86_xop_vpcomgtuq:
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case Intrinsic::x86_xop_vpcomgeb:
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case Intrinsic::x86_xop_vpcomgew:
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case Intrinsic::x86_xop_vpcomged:
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case Intrinsic::x86_xop_vpcomgeq:
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case Intrinsic::x86_xop_vpcomgeub:
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case Intrinsic::x86_xop_vpcomgeuw:
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case Intrinsic::x86_xop_vpcomgeud:
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case Intrinsic::x86_xop_vpcomgeuq:
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case Intrinsic::x86_xop_vpcomeqb:
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case Intrinsic::x86_xop_vpcomeqw:
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case Intrinsic::x86_xop_vpcomeqd:
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case Intrinsic::x86_xop_vpcomeqq:
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case Intrinsic::x86_xop_vpcomequb:
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case Intrinsic::x86_xop_vpcomequw:
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case Intrinsic::x86_xop_vpcomequd:
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case Intrinsic::x86_xop_vpcomequq:
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case Intrinsic::x86_xop_vpcomneb:
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case Intrinsic::x86_xop_vpcomnew:
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case Intrinsic::x86_xop_vpcomned:
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case Intrinsic::x86_xop_vpcomneq:
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case Intrinsic::x86_xop_vpcomneub:
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case Intrinsic::x86_xop_vpcomneuw:
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case Intrinsic::x86_xop_vpcomneud:
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case Intrinsic::x86_xop_vpcomneuq:
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case Intrinsic::x86_xop_vpcomfalseb:
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case Intrinsic::x86_xop_vpcomfalsew:
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case Intrinsic::x86_xop_vpcomfalsed:
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case Intrinsic::x86_xop_vpcomfalseq:
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case Intrinsic::x86_xop_vpcomfalseub:
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case Intrinsic::x86_xop_vpcomfalseuw:
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case Intrinsic::x86_xop_vpcomfalseud:
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case Intrinsic::x86_xop_vpcomfalseuq:
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case Intrinsic::x86_xop_vpcomtrueb:
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case Intrinsic::x86_xop_vpcomtruew:
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case Intrinsic::x86_xop_vpcomtrued:
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case Intrinsic::x86_xop_vpcomtrueq:
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case Intrinsic::x86_xop_vpcomtrueub:
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case Intrinsic::x86_xop_vpcomtrueuw:
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case Intrinsic::x86_xop_vpcomtrueud:
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case Intrinsic::x86_xop_vpcomtrueuq: {
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unsigned CC = 0;
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unsigned Opc = 0;
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switch (IntNo) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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case Intrinsic::x86_xop_vpcomltb:
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case Intrinsic::x86_xop_vpcomltw:
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case Intrinsic::x86_xop_vpcomltd:
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case Intrinsic::x86_xop_vpcomltq:
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CC = 0;
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Opc = X86ISD::VPCOM;
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break;
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case Intrinsic::x86_xop_vpcomltub:
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case Intrinsic::x86_xop_vpcomltuw:
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case Intrinsic::x86_xop_vpcomltud:
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case Intrinsic::x86_xop_vpcomltuq:
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CC = 0;
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Opc = X86ISD::VPCOMU;
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break;
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case Intrinsic::x86_xop_vpcomleb:
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case Intrinsic::x86_xop_vpcomlew:
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case Intrinsic::x86_xop_vpcomled:
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case Intrinsic::x86_xop_vpcomleq:
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CC = 1;
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Opc = X86ISD::VPCOM;
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break;
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case Intrinsic::x86_xop_vpcomleub:
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case Intrinsic::x86_xop_vpcomleuw:
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case Intrinsic::x86_xop_vpcomleud:
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case Intrinsic::x86_xop_vpcomleuq:
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CC = 1;
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Opc = X86ISD::VPCOMU;
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break;
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case Intrinsic::x86_xop_vpcomgtb:
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case Intrinsic::x86_xop_vpcomgtw:
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case Intrinsic::x86_xop_vpcomgtd:
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case Intrinsic::x86_xop_vpcomgtq:
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CC = 2;
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Opc = X86ISD::VPCOM;
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break;
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case Intrinsic::x86_xop_vpcomgtub:
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case Intrinsic::x86_xop_vpcomgtuw:
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case Intrinsic::x86_xop_vpcomgtud:
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case Intrinsic::x86_xop_vpcomgtuq:
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CC = 2;
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Opc = X86ISD::VPCOMU;
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break;
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case Intrinsic::x86_xop_vpcomgeb:
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case Intrinsic::x86_xop_vpcomgew:
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case Intrinsic::x86_xop_vpcomged:
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case Intrinsic::x86_xop_vpcomgeq:
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CC = 3;
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Opc = X86ISD::VPCOM;
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break;
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case Intrinsic::x86_xop_vpcomgeub:
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case Intrinsic::x86_xop_vpcomgeuw:
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case Intrinsic::x86_xop_vpcomgeud:
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case Intrinsic::x86_xop_vpcomgeuq:
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CC = 3;
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Opc = X86ISD::VPCOMU;
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break;
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case Intrinsic::x86_xop_vpcomeqb:
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case Intrinsic::x86_xop_vpcomeqw:
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case Intrinsic::x86_xop_vpcomeqd:
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case Intrinsic::x86_xop_vpcomeqq:
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CC = 4;
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Opc = X86ISD::VPCOM;
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break;
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case Intrinsic::x86_xop_vpcomequb:
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case Intrinsic::x86_xop_vpcomequw:
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case Intrinsic::x86_xop_vpcomequd:
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case Intrinsic::x86_xop_vpcomequq:
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CC = 4;
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Opc = X86ISD::VPCOMU;
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break;
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case Intrinsic::x86_xop_vpcomneb:
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case Intrinsic::x86_xop_vpcomnew:
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case Intrinsic::x86_xop_vpcomned:
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case Intrinsic::x86_xop_vpcomneq:
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CC = 5;
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Opc = X86ISD::VPCOM;
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break;
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case Intrinsic::x86_xop_vpcomneub:
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case Intrinsic::x86_xop_vpcomneuw:
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case Intrinsic::x86_xop_vpcomneud:
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case Intrinsic::x86_xop_vpcomneuq:
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CC = 5;
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Opc = X86ISD::VPCOMU;
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break;
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case Intrinsic::x86_xop_vpcomfalseb:
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case Intrinsic::x86_xop_vpcomfalsew:
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case Intrinsic::x86_xop_vpcomfalsed:
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case Intrinsic::x86_xop_vpcomfalseq:
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CC = 6;
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Opc = X86ISD::VPCOM;
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break;
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case Intrinsic::x86_xop_vpcomfalseub:
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case Intrinsic::x86_xop_vpcomfalseuw:
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case Intrinsic::x86_xop_vpcomfalseud:
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case Intrinsic::x86_xop_vpcomfalseuq:
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CC = 6;
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Opc = X86ISD::VPCOMU;
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break;
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case Intrinsic::x86_xop_vpcomtrueb:
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case Intrinsic::x86_xop_vpcomtruew:
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case Intrinsic::x86_xop_vpcomtrued:
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case Intrinsic::x86_xop_vpcomtrueq:
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CC = 7;
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Opc = X86ISD::VPCOM;
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break;
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case Intrinsic::x86_xop_vpcomtrueub:
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case Intrinsic::x86_xop_vpcomtrueuw:
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case Intrinsic::x86_xop_vpcomtrueud:
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case Intrinsic::x86_xop_vpcomtrueuq:
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CC = 7;
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Opc = X86ISD::VPCOMU;
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break;
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}
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SDValue LHS = Op.getOperand(1);
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SDValue RHS = Op.getOperand(2);
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return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
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DAG.getConstant(CC, MVT::i8));
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}
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// Arithmetic intrinsics.
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case Intrinsic::x86_sse3_hadd_ps:
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case Intrinsic::x86_sse3_hadd_pd:
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@ -234,6 +234,9 @@ namespace llvm {
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// PCMP* - Vector integer comparisons.
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PCMPEQ, PCMPGT,
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// VPCOM, VPCOMU - XOP Vector integer comparisons.
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VPCOM, VPCOMU,
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// ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
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ADD, SUB, ADC, SBB, SMUL,
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INC, DEC, OR, XOR, AND,
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@ -99,6 +99,13 @@ def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
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def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
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def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
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def X86vpcom : SDNode<"X86ISD::VPCOM",
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SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>>;
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def X86vpcomu : SDNode<"X86ISD::VPCOMU",
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SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>>;
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// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
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// translated into one of the target nodes below during lowering.
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// Note: this is a work in progress...
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@ -117,14 +117,17 @@ let isAsmParserOnly = 1 in {
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}
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multiclass xop3opimm<bits<8> opc, string OpcodeStr> {
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def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX;
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins f128mem:$src1, i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX;
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let neverHasSideEffects = 1 in {
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def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX;
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let mayLoad = 1 in
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins f128mem:$src1, i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX;
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}
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}
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let isAsmParserOnly = 1 in {
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@ -167,74 +170,92 @@ let isAsmParserOnly = 1 in {
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}
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// Instruction where second source can be memory, third must be imm8
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multiclass xop4opimm<bits<8> opc, string OpcodeStr> {
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multiclass xop4opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType VT> {
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def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V;
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[(set VR128:$dst,
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(VT (OpNode VR128:$src1, VR128:$src2, imm:$src3)))]>, VEX_4V;
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V;
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[(set VR128:$dst,
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(VT (OpNode VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
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imm:$src3)))]>, VEX_4V;
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}
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let isAsmParserOnly = 1 in {
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defm VPCOMW : xop4opimm<0xCD, "vpcomw">;
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defm VPCOMUW : xop4opimm<0xED, "vpcomuw">;
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defm VPCOMUQ : xop4opimm<0xEF, "vpcomuq">;
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defm VPCOMUD : xop4opimm<0xEE, "vpcomud">;
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defm VPCOMUB : xop4opimm<0xEC, "vpcomub">;
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defm VPCOMQ : xop4opimm<0xCF, "vpcomq">;
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defm VPCOMD : xop4opimm<0xCE, "vpcomd">;
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defm VPCOMB : xop4opimm<0xCC, "vpcomb">;
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defm VPCOMB : xop4opimm<0xCC, "vpcomb", X86vpcom, v16i8>;
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defm VPCOMW : xop4opimm<0xCD, "vpcomw", X86vpcom, v8i16>;
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defm VPCOMD : xop4opimm<0xCE, "vpcomd", X86vpcom, v4i32>;
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defm VPCOMQ : xop4opimm<0xCF, "vpcomq", X86vpcom, v2i64>;
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defm VPCOMUB : xop4opimm<0xEC, "vpcomub", X86vpcomu, v16i8>;
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defm VPCOMUW : xop4opimm<0xED, "vpcomuw", X86vpcomu, v8i16>;
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defm VPCOMUD : xop4opimm<0xEE, "vpcomud", X86vpcomu, v4i32>;
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defm VPCOMUQ : xop4opimm<0xEF, "vpcomuq", X86vpcomu, v2i64>;
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}
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// Instruction where either second or third source can be memory
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multiclass xop4op<bits<8> opc, string OpcodeStr> {
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multiclass xop4op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
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def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM;
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[(set VR128:$dst, (Int VR128:$src1, VR128:$src2, VR128:$src3))]>,
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VEX_4V, VEX_I8IMM;
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def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
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[(set VR128:$dst,
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(Int VR128:$src1, VR128:$src2,
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(bitconvert (memopv2i64 addr:$src3))))]>,
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VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
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def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM;
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[(set VR128:$dst,
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(Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
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VR128:$src3))]>,
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VEX_4V, VEX_I8IMM;
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}
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let isAsmParserOnly = 1 in {
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defm VPPERM : xop4op<0xA3, "vpperm">;
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defm VPCMOV : xop4op<0xA2, "vpcmov">;
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defm VPPERM : xop4op<0xA3, "vpperm", int_x86_xop_vpperm>;
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defm VPCMOV : xop4op<0xA2, "vpcmov", int_x86_xop_vpcmov>;
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}
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multiclass xop4op256<bits<8> opc, string OpcodeStr> {
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multiclass xop4op256<bits<8> opc, string OpcodeStr, Intrinsic Int> {
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def rrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM;
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[(set VR256:$dst, (Int VR256:$src1, VR256:$src2, VR256:$src3))]>,
|
||||
VEX_4V, VEX_I8IMM;
|
||||
def rmY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
|
||||
(ins VR256:$src1, VR256:$src2, f256mem:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
||||
[]>, VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
|
||||
[(set VR256:$dst,
|
||||
(Int VR256:$src1, VR256:$src2,
|
||||
(bitconvert (memopv4i64 addr:$src3))))]>,
|
||||
VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
|
||||
def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
|
||||
(ins VR256:$src1, f256mem:$src2, VR256:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
||||
[]>, VEX_4V, VEX_I8IMM;
|
||||
[(set VR256:$dst,
|
||||
(Int VR256:$src1, (bitconvert (memopv4i64 addr:$src2)),
|
||||
VR256:$src3))]>,
|
||||
VEX_4V, VEX_I8IMM;
|
||||
}
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm VPCMOV : xop4op256<0xA2, "vpcmov">;
|
||||
defm VPCMOV : xop4op256<0xA2, "vpcmov", int_x86_xop_vpcmov_256>;
|
||||
}
|
||||
|
||||
multiclass xop5op<bits<8> opc, string OpcodeStr, Intrinsic Int128,
|
||||
|
|
@ -287,427 +308,6 @@ defm VPERMIL2PS : xop5op<0x48, "vpermil2ps", int_x86_xop_vpermil2ps,
|
|||
// XOP Intrinsics patterns
|
||||
|
||||
let Predicates = [HasXOP] in {
|
||||
// VPCOM EQ
|
||||
def : Pat<(int_x86_xop_vpcomeqw VR128:$src1, VR128:$src2),
|
||||
(VPCOMWri VR128:$src1, VR128:$src2, (i8 4))>;
|
||||
def : Pat<(int_x86_xop_vpcomeqw VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMWmi VR128:$src1, addr:$src2, (i8 4))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomequw VR128:$src1, VR128:$src2),
|
||||
(VPCOMUWri VR128:$src1, VR128:$src2, (i8 4))>;
|
||||
def : Pat<(int_x86_xop_vpcomequw VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUWmi VR128:$src1, addr:$src2, (i8 4))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomequq VR128:$src1, VR128:$src2),
|
||||
(VPCOMUQri VR128:$src1, VR128:$src2, (i8 4))>;
|
||||
def : Pat<(int_x86_xop_vpcomequq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUQmi VR128:$src1, addr:$src2, (i8 4))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomequd VR128:$src1, VR128:$src2),
|
||||
(VPCOMUDri VR128:$src1, VR128:$src2, (i8 4))>;
|
||||
def : Pat<(int_x86_xop_vpcomequd VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUDmi VR128:$src1, addr:$src2, (i8 4))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomequb VR128:$src1, VR128:$src2),
|
||||
(VPCOMUBri VR128:$src1, VR128:$src2, (i8 4))>;
|
||||
def : Pat<(int_x86_xop_vpcomequb VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUBmi VR128:$src1, addr:$src2, (i8 4))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomeqq VR128:$src1, VR128:$src2),
|
||||
(VPCOMQri VR128:$src1, VR128:$src2, (i8 4))>;
|
||||
def : Pat<(int_x86_xop_vpcomeqq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMQmi VR128:$src1, addr:$src2, (i8 4))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomeqd VR128:$src1, VR128:$src2),
|
||||
(VPCOMDri VR128:$src1, VR128:$src2, (i8 4))>;
|
||||
def : Pat<(int_x86_xop_vpcomeqd VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMDmi VR128:$src1, addr:$src2, (i8 4))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomeqb VR128:$src1, VR128:$src2),
|
||||
(VPCOMBri VR128:$src1, VR128:$src2, (i8 4))>;
|
||||
def : Pat<(int_x86_xop_vpcomeqb VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMBmi VR128:$src1, addr:$src2, (i8 4))>;
|
||||
|
||||
// VPCOM FALSE
|
||||
def : Pat<(int_x86_xop_vpcomfalsew VR128:$src1, VR128:$src2),
|
||||
(VPCOMWri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomfalsew VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMWmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomfalseuw VR128:$src1, VR128:$src2),
|
||||
(VPCOMUWri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomfalseuw VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUWmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomfalseuq VR128:$src1, VR128:$src2),
|
||||
(VPCOMUQri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomfalseuq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUQmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomfalseud VR128:$src1, VR128:$src2),
|
||||
(VPCOMUDri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomfalseud VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUDmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomfalseub VR128:$src1, VR128:$src2),
|
||||
(VPCOMUBri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomfalseub VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUBmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomfalseq VR128:$src1, VR128:$src2),
|
||||
(VPCOMQri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomfalseq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMQmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomfalsed VR128:$src1, VR128:$src2),
|
||||
(VPCOMDri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomfalsed VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMDmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomfalseb VR128:$src1, VR128:$src2),
|
||||
(VPCOMBri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomfalseb VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMBmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
// VPCOM GE
|
||||
def : Pat<(int_x86_xop_vpcomgew VR128:$src1, VR128:$src2),
|
||||
(VPCOMWri VR128:$src1, VR128:$src2, (i8 3))>;
|
||||
def : Pat<(int_x86_xop_vpcomgew VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMWmi VR128:$src1, addr:$src2, (i8 3))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgeuw VR128:$src1, VR128:$src2),
|
||||
(VPCOMUWri VR128:$src1, VR128:$src2, (i8 3))>;
|
||||
def : Pat<(int_x86_xop_vpcomgeuw VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUWmi VR128:$src1, addr:$src2, (i8 3))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgeuq VR128:$src1, VR128:$src2),
|
||||
(VPCOMUQri VR128:$src1, VR128:$src2, (i8 3))>;
|
||||
def : Pat<(int_x86_xop_vpcomgeuq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUQmi VR128:$src1, addr:$src2, (i8 3))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgeud VR128:$src1, VR128:$src2),
|
||||
(VPCOMUDri VR128:$src1, VR128:$src2, (i8 3))>;
|
||||
def : Pat<(int_x86_xop_vpcomgeud VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUDmi VR128:$src1, addr:$src2, (i8 3))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgeub VR128:$src1, VR128:$src2),
|
||||
(VPCOMUBri VR128:$src1, VR128:$src2, (i8 3))>;
|
||||
def : Pat<(int_x86_xop_vpcomgeub VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUBmi VR128:$src1, addr:$src2, (i8 3))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgeq VR128:$src1, VR128:$src2),
|
||||
(VPCOMQri VR128:$src1, VR128:$src2, (i8 3))>;
|
||||
def : Pat<(int_x86_xop_vpcomgeq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMQmi VR128:$src1, addr:$src2, (i8 3))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomged VR128:$src1, VR128:$src2),
|
||||
(VPCOMDri VR128:$src1, VR128:$src2, (i8 3))>;
|
||||
def : Pat<(int_x86_xop_vpcomged VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMDmi VR128:$src1, addr:$src2, (i8 3))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgeb VR128:$src1, VR128:$src2),
|
||||
(VPCOMBri VR128:$src1, VR128:$src2, (i8 3))>;
|
||||
def : Pat<(int_x86_xop_vpcomgeb VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMBmi VR128:$src1, addr:$src2, (i8 3))>;
|
||||
|
||||
// VPCOM GT
|
||||
def : Pat<(int_x86_xop_vpcomgtw VR128:$src1, VR128:$src2),
|
||||
(VPCOMWri VR128:$src1, VR128:$src2, (i8 2))>;
|
||||
def : Pat<(int_x86_xop_vpcomgtw VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMWmi VR128:$src1, addr:$src2, (i8 2))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgtuw VR128:$src1, VR128:$src2),
|
||||
(VPCOMUWri VR128:$src1, VR128:$src2, (i8 2))>;
|
||||
def : Pat<(int_x86_xop_vpcomgtuw VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUWmi VR128:$src1, addr:$src2, (i8 2))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgtuq VR128:$src1, VR128:$src2),
|
||||
(VPCOMUQri VR128:$src1, VR128:$src2, (i8 2))>;
|
||||
def : Pat<(int_x86_xop_vpcomgtuq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUQmi VR128:$src1, addr:$src2, (i8 2))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgtud VR128:$src1, VR128:$src2),
|
||||
(VPCOMUDri VR128:$src1, VR128:$src2, (i8 2))>;
|
||||
def : Pat<(int_x86_xop_vpcomgtud VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUDmi VR128:$src1, addr:$src2, (i8 2))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgtub VR128:$src1, VR128:$src2),
|
||||
(VPCOMUBri VR128:$src1, VR128:$src2, (i8 2))>;
|
||||
def : Pat<(int_x86_xop_vpcomgtub VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUBmi VR128:$src1, addr:$src2, (i8 2))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgtq VR128:$src1, VR128:$src2),
|
||||
(VPCOMQri VR128:$src1, VR128:$src2, (i8 2))>;
|
||||
def : Pat<(int_x86_xop_vpcomgtq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMQmi VR128:$src1, addr:$src2, (i8 2))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgtd VR128:$src1, VR128:$src2),
|
||||
(VPCOMDri VR128:$src1, VR128:$src2, (i8 2))>;
|
||||
def : Pat<(int_x86_xop_vpcomgtd VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMDmi VR128:$src1, addr:$src2, (i8 2))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomgtb VR128:$src1, VR128:$src2),
|
||||
(VPCOMBri VR128:$src1, VR128:$src2, (i8 2))>;
|
||||
def : Pat<(int_x86_xop_vpcomgtb VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMBmi VR128:$src1, addr:$src2, (i8 2))>;
|
||||
|
||||
// VPCOM LE
|
||||
def : Pat<(int_x86_xop_vpcomlew VR128:$src1, VR128:$src2),
|
||||
(VPCOMWri VR128:$src1, VR128:$src2, (i8 1))>;
|
||||
def : Pat<(int_x86_xop_vpcomlew VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMWmi VR128:$src1, addr:$src2, (i8 1))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomleuw VR128:$src1, VR128:$src2),
|
||||
(VPCOMUWri VR128:$src1, VR128:$src2, (i8 1))>;
|
||||
def : Pat<(int_x86_xop_vpcomleuw VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUWmi VR128:$src1, addr:$src2, (i8 1))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomleuq VR128:$src1, VR128:$src2),
|
||||
(VPCOMUQri VR128:$src1, VR128:$src2, (i8 1))>;
|
||||
def : Pat<(int_x86_xop_vpcomleuq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUQmi VR128:$src1, addr:$src2, (i8 1))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomleud VR128:$src1, VR128:$src2),
|
||||
(VPCOMUDri VR128:$src1, VR128:$src2, (i8 1))>;
|
||||
def : Pat<(int_x86_xop_vpcomleud VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUDmi VR128:$src1, addr:$src2, (i8 1))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomleub VR128:$src1, VR128:$src2),
|
||||
(VPCOMUBri VR128:$src1, VR128:$src2, (i8 1))>;
|
||||
def : Pat<(int_x86_xop_vpcomleub VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUBmi VR128:$src1, addr:$src2, (i8 1))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomleq VR128:$src1, VR128:$src2),
|
||||
(VPCOMQri VR128:$src1, VR128:$src2, (i8 1))>;
|
||||
def : Pat<(int_x86_xop_vpcomleq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMQmi VR128:$src1, addr:$src2, (i8 1))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomled VR128:$src1, VR128:$src2),
|
||||
(VPCOMDri VR128:$src1, VR128:$src2, (i8 1))>;
|
||||
def : Pat<(int_x86_xop_vpcomled VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMDmi VR128:$src1, addr:$src2, (i8 1))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomleb VR128:$src1, VR128:$src2),
|
||||
(VPCOMBri VR128:$src1, VR128:$src2, (i8 1))>;
|
||||
def : Pat<(int_x86_xop_vpcomleb VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMBmi VR128:$src1, addr:$src2, (i8 1))>;
|
||||
|
||||
// VPCOM LT
|
||||
def : Pat<(int_x86_xop_vpcomltw VR128:$src1, VR128:$src2),
|
||||
(VPCOMWri VR128:$src1, VR128:$src2, (i8 0))>;
|
||||
def : Pat<(int_x86_xop_vpcomltw VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMWmi VR128:$src1, addr:$src2, (i8 0))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomltuw VR128:$src1, VR128:$src2),
|
||||
(VPCOMUWri VR128:$src1, VR128:$src2, (i8 0))>;
|
||||
def : Pat<(int_x86_xop_vpcomltuw VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUWmi VR128:$src1, addr:$src2, (i8 0))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomltuq VR128:$src1, VR128:$src2),
|
||||
(VPCOMUQri VR128:$src1, VR128:$src2, (i8 0))>;
|
||||
def : Pat<(int_x86_xop_vpcomltuq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUQmi VR128:$src1, addr:$src2, (i8 0))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomltud VR128:$src1, VR128:$src2),
|
||||
(VPCOMUDri VR128:$src1, VR128:$src2, (i8 0))>;
|
||||
def : Pat<(int_x86_xop_vpcomltud VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUDmi VR128:$src1, addr:$src2, (i8 0))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomltub VR128:$src1, VR128:$src2),
|
||||
(VPCOMUBri VR128:$src1, VR128:$src2, (i8 0))>;
|
||||
def : Pat<(int_x86_xop_vpcomltub VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUBmi VR128:$src1, addr:$src2, (i8 0))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomltq VR128:$src1, VR128:$src2),
|
||||
(VPCOMQri VR128:$src1, VR128:$src2, (i8 0))>;
|
||||
def : Pat<(int_x86_xop_vpcomltq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMQmi VR128:$src1, addr:$src2, (i8 0))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomltd VR128:$src1, VR128:$src2),
|
||||
(VPCOMDri VR128:$src1, VR128:$src2, (i8 0))>;
|
||||
def : Pat<(int_x86_xop_vpcomltd VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMDmi VR128:$src1, addr:$src2, (i8 0))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomltb VR128:$src1, VR128:$src2),
|
||||
(VPCOMBri VR128:$src1, VR128:$src2, (i8 0))>;
|
||||
def : Pat<(int_x86_xop_vpcomltb VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMBmi VR128:$src1, addr:$src2, (i8 0))>;
|
||||
|
||||
// VPCOM NE
|
||||
def : Pat<(int_x86_xop_vpcomnew VR128:$src1, VR128:$src2),
|
||||
(VPCOMWri VR128:$src1, VR128:$src2, (i8 5))>;
|
||||
def : Pat<(int_x86_xop_vpcomnew VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMWmi VR128:$src1, addr:$src2, (i8 5))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomneuw VR128:$src1, VR128:$src2),
|
||||
(VPCOMUWri VR128:$src1, VR128:$src2, (i8 5))>;
|
||||
def : Pat<(int_x86_xop_vpcomneuw VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUWmi VR128:$src1, addr:$src2, (i8 5))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomneuq VR128:$src1, VR128:$src2),
|
||||
(VPCOMUQri VR128:$src1, VR128:$src2, (i8 5))>;
|
||||
def : Pat<(int_x86_xop_vpcomneuq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUQmi VR128:$src1, addr:$src2, (i8 5))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomneud VR128:$src1, VR128:$src2),
|
||||
(VPCOMUDri VR128:$src1, VR128:$src2, (i8 5))>;
|
||||
def : Pat<(int_x86_xop_vpcomneud VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUDmi VR128:$src1, addr:$src2, (i8 5))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomneub VR128:$src1, VR128:$src2),
|
||||
(VPCOMUBri VR128:$src1, VR128:$src2, (i8 5))>;
|
||||
def : Pat<(int_x86_xop_vpcomneub VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUBmi VR128:$src1, addr:$src2, (i8 5))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomneq VR128:$src1, VR128:$src2),
|
||||
(VPCOMQri VR128:$src1, VR128:$src2, (i8 5))>;
|
||||
def : Pat<(int_x86_xop_vpcomneq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMQmi VR128:$src1, addr:$src2, (i8 5))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomned VR128:$src1, VR128:$src2),
|
||||
(VPCOMDri VR128:$src1, VR128:$src2, (i8 5))>;
|
||||
def : Pat<(int_x86_xop_vpcomned VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMDmi VR128:$src1, addr:$src2, (i8 5))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomneb VR128:$src1, VR128:$src2),
|
||||
(VPCOMBri VR128:$src1, VR128:$src2, (i8 5))>;
|
||||
def : Pat<(int_x86_xop_vpcomneb VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMBmi VR128:$src1, addr:$src2, (i8 5))>;
|
||||
|
||||
// VPCOM TRUE
|
||||
def : Pat<(int_x86_xop_vpcomtruew VR128:$src1, VR128:$src2),
|
||||
(VPCOMWri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomtruew VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMWmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomtrueuw VR128:$src1, VR128:$src2),
|
||||
(VPCOMUWri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomtrueuw VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUWmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomtrueuq VR128:$src1, VR128:$src2),
|
||||
(VPCOMUQri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomtrueuq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUQmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomtrueud VR128:$src1, VR128:$src2),
|
||||
(VPCOMUDri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomtrueud VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUDmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomtrueub VR128:$src1, VR128:$src2),
|
||||
(VPCOMUBri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomtrueub VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMUBmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomtrueq VR128:$src1, VR128:$src2),
|
||||
(VPCOMQri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomtrueq VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMQmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomtrued VR128:$src1, VR128:$src2),
|
||||
(VPCOMDri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomtrued VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMDmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
def : Pat<(int_x86_xop_vpcomtrueb VR128:$src1, VR128:$src2),
|
||||
(VPCOMBri VR128:$src1, VR128:$src2, (i8 6))>;
|
||||
def : Pat<(int_x86_xop_vpcomtrueb VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2))),
|
||||
(VPCOMBmi VR128:$src1, addr:$src2, (i8 6))>;
|
||||
|
||||
// VPPERM
|
||||
def : Pat<(int_x86_xop_vpperm VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VPPERMrr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpperm VR128:$src1, VR128:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPPERMrm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpperm VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
|
||||
VR128:$src3),
|
||||
(VPPERMmr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
|
||||
// VPCMOV
|
||||
def : Pat<(int_x86_xop_vpcmov VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VPCMOVrr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov VR128:$src1, VR128:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
|
||||
VR128:$src3),
|
||||
(VPCMOVmr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VPCMOVrrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_256 VR256:$src1, VR256:$src2,
|
||||
(bitconvert (memopv4i64 addr:$src3))),
|
||||
(VPCMOVrmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_256 VR256:$src1,
|
||||
(bitconvert (memopv4i64 addr:$src2)),
|
||||
VR256:$src3),
|
||||
(VPCMOVmrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
|
||||
// VPCMOV di
|
||||
def : Pat<(int_x86_xop_vpcmov_v2di VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VPCMOVrr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue