diff --git a/llvm/include/llvm/CodeGen/RegisterScavenging.h b/llvm/include/llvm/CodeGen/RegisterScavenging.h
index 117539a498e0..33d00a744359 100644
--- a/llvm/include/llvm/CodeGen/RegisterScavenging.h
+++ b/llvm/include/llvm/CodeGen/RegisterScavenging.h
@@ -27,6 +27,7 @@ class TargetRegisterClass;
 class RegScavenger {
   MachineBasicBlock *MBB;
   MachineBasicBlock::iterator MBBI;
+  bool MBBIInited;
   unsigned NumPhysRegs;
 
   /// RegStates - The current state of all the physical registers immediately
@@ -42,6 +43,11 @@ public:
   void forward();
   void backward();
 
+  /// forward / backward - Move the internal MBB iterator and update register
+  /// states until it has reached but not processed the specific iterator.
+  void forward(MachineBasicBlock::iterator I);
+  void backward(MachineBasicBlock::iterator I);
+
   /// isReserved - Returns true if a register is reserved. It is never "unused".
   bool isReserved(unsigned Reg) const { return ReservedRegs[Reg]; }
 
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 5318ce5855e4..e9d7d837e89a 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -455,7 +455,7 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) {
         }
       // Update register states.
       if (MRI.requiresRegisterScavenging())
-        RS.forward();
+        RS.forward(I);
     }
   }
 }
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index 9135edcfb9e2..3ee0f97f779c 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -22,10 +22,11 @@
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/ADT/STLExtras.h"
 using namespace llvm;
 
 RegScavenger::RegScavenger(MachineBasicBlock *mbb)
-  : MBB(mbb), MBBI(mbb->begin()) {
+  : MBB(mbb), MBBIInited(false) {
   const MachineFunction &MF = *MBB->getParent();
   const TargetMachine &TM = MF.getTarget();
   const MRegisterInfo *RegInfo = TM.getRegisterInfo();
@@ -52,6 +53,14 @@ RegScavenger::RegScavenger(MachineBasicBlock *mbb)
 }
 
 void RegScavenger::forward() {
+  assert(MBBI != MBB->end() && "Already at the end of the basic block!");
+  // Move ptr forward.
+  if (!MBBIInited) {
+    MBBI = MBB->begin();
+    MBBIInited = true;
+  } else
+    MBBI = next(MBBI);
+
   MachineInstr *MI = MBBI;
   // Process uses first.
   BitVector ChangedRegs(NumPhysRegs);
@@ -86,12 +95,14 @@ void RegScavenger::forward() {
     if (!MO.isDead())
       setUsed(Reg);
   }
-
-  ++MBBI;
 }
 
 void RegScavenger::backward() {
-  MachineInstr *MI = --MBBI;
+  assert(MBBI != MBB->begin() && "Already at start of basic block!");
+  // Move ptr backward.
+  MBBI = prior(MBBI);
+
+  MachineInstr *MI = MBBI;
   // Process defs first.
   const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
@@ -122,6 +133,16 @@ void RegScavenger::backward() {
   setUsed(ChangedRegs);
 }
 
+void RegScavenger::forward(MachineBasicBlock::iterator I) {
+  while (MBBI != I)
+    forward();
+}
+
+void RegScavenger::backward(MachineBasicBlock::iterator I) {
+  while (MBBI != I)
+    backward();
+}
+
 /// CreateRegClassMask - Set the bits that represent the registers in the
 /// TargetRegisterClass.
 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {