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[PowerPC] Implement instruction definitions/MC Tests for xvcvspbf16 and xvcvbf16spn 

This patch adds the td instruction definitions of the xvcvspbf16 and xvcvbf16spn
instructions, along with their respective MC tests.

Differential Revision: https://reviews.llvm.org/D86794
This commit is contained in:
Amy Kwan 2020-09-01 10:15:45 -05:00
parent 1a633e72f6
commit ca2227c1b3
3 changed files with 17 additions and 0 deletions
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5
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
View File

@ -1300,6 +1300,11 @@ let Predicates = [IsISA3_1] in {
def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
}
let Predicates = [IsISA3_1, HasVSX] in {
def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>;
def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>;
}
//---------------------------- Anonymous Patterns ----------------------------//
let Predicates = [IsISA3_1] in {
// Exploit the vector multiply high instructions using intrinsics.

6
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
View File

@ -542,3 +542,9 @@
# CHECK: vstrihl. 2, 2
0x10 0x42 0x14 0x0d
# CHECK: xvcvspbf16 33, 34
0xf0 0x31 0x17 0x6f
# CHECK: xvcvbf16spn 33, 34
0xf0 0x30 0x17 0x6f

6
llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
View File

@ -666,3 +666,9 @@
# CHECK-BE: vstrihl. 2, 2 # encoding: [0x10,0x42,0x14,0x0d]
# CHECK-LE: vstrihl. 2, 2 # encoding: [0x0d,0x14,0x42,0x10]
vstrihl. 2, 2
# CHECK-BE: xvcvspbf16 33, 34 # encoding: [0xf0,0x31,0x17,0x6f]
# CHECK-LE: xvcvspbf16 33, 34 # encoding: [0x6f,0x17,0x31,0xf0]
xvcvspbf16 33, 34
# CHECK-BE: xvcvbf16spn 33, 34 # encoding: [0xf0,0x30,0x17,0x6f]
# CHECK-LE: xvcvbf16spn 33, 34 # encoding: [0x6f,0x17,0x30,0xf0]
xvcvbf16spn 33, 34