From ca2227c1b3f52611de7d051ffea91b0c6c21e1ac Mon Sep 17 00:00:00 2001 From: Amy Kwan Date: Tue, 1 Sep 2020 10:15:45 -0500 Subject: [PATCH] [PowerPC] Implement instruction definitions/MC Tests for xvcvspbf16 and xvcvbf16spn This patch adds the td instruction definitions of the xvcvspbf16 and xvcvbf16spn instructions, along with their respective MC tests. Differential Revision: https://reviews.llvm.org/D86794 --- llvm/lib/Target/PowerPC/PPCInstrPrefix.td | 5 +++++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt | 6 ++++++ llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s | 6 ++++++ 3 files changed, 17 insertions(+) diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td index f5176850836e..fc4e57ec04f6 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -1300,6 +1300,11 @@ let Predicates = [IsISA3_1] in { def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>; } +let Predicates = [IsISA3_1, HasVSX] in { + def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>; + def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>; +} + //---------------------------- Anonymous Patterns ----------------------------// let Predicates = [IsISA3_1] in { // Exploit the vector multiply high instructions using intrinsics. diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt index eb17515de0ca..a07f10d1bf6b 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt @@ -542,3 +542,9 @@ # CHECK: vstrihl. 2, 2 0x10 0x42 0x14 0x0d + +# CHECK: xvcvspbf16 33, 34 +0xf0 0x31 0x17 0x6f + +# CHECK: xvcvbf16spn 33, 34 +0xf0 0x30 0x17 0x6f diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s index d925f717d054..29e9a7a74bf6 100644 --- a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s +++ b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s @@ -666,3 +666,9 @@ # CHECK-BE: vstrihl. 2, 2 # encoding: [0x10,0x42,0x14,0x0d] # CHECK-LE: vstrihl. 2, 2 # encoding: [0x0d,0x14,0x42,0x10] vstrihl. 2, 2 +# CHECK-BE: xvcvspbf16 33, 34 # encoding: [0xf0,0x31,0x17,0x6f] +# CHECK-LE: xvcvspbf16 33, 34 # encoding: [0x6f,0x17,0x31,0xf0] + xvcvspbf16 33, 34 +# CHECK-BE: xvcvbf16spn 33, 34 # encoding: [0xf0,0x30,0x17,0x6f] +# CHECK-LE: xvcvbf16spn 33, 34 # encoding: [0x6f,0x17,0x30,0xf0] + xvcvbf16spn 33, 34