forked from OSchip/llvm-project
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ca21cc8b13
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@ -968,7 +968,7 @@ SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
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VT, SDValue(Pair, 0), V1, SubReg1);
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}
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/// PairDRegs - Form a quad register pair from a pair of Q registers.
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/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
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///
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SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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@ -978,7 +978,7 @@ SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
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}
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/// QuadDRegs - Form a octo register from a quad of D registers.
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/// QuadDRegs - Form 4 consecutive D registers.
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///
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SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
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SDValue V2, SDValue V3) {
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