forked from OSchip/llvm-project
[AMDGPU] SILoadStoreOptimizer: simplify OptimizeListAgain test
At this point CI represents the combined access (original CI combined with Paired) so it doesn't make any sense to add in Paired.width again. NFCI.
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@ -2128,42 +2128,42 @@ SILoadStoreOptimizer::optimizeInstsWithSameBaseAddr(
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MachineBasicBlock::iterator NewMI =
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mergeSBufferLoadImmPair(CI, Paired, InstsToMove);
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CI.setMI(NewMI, *this);
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OptimizeListAgain |= (CI.Width + Paired.Width) < 8;
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OptimizeListAgain |= CI.Width < 8;
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break;
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}
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case BUFFER_LOAD: {
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MachineBasicBlock::iterator NewMI =
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mergeBufferLoadPair(CI, Paired, InstsToMove);
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CI.setMI(NewMI, *this);
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OptimizeListAgain |= (CI.Width + Paired.Width) < 4;
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OptimizeListAgain |= CI.Width < 4;
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break;
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}
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case BUFFER_STORE: {
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MachineBasicBlock::iterator NewMI =
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mergeBufferStorePair(CI, Paired, InstsToMove);
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CI.setMI(NewMI, *this);
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OptimizeListAgain |= (CI.Width + Paired.Width) < 4;
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OptimizeListAgain |= CI.Width < 4;
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break;
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}
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case MIMG: {
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MachineBasicBlock::iterator NewMI =
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mergeImagePair(CI, Paired, InstsToMove);
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CI.setMI(NewMI, *this);
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OptimizeListAgain |= (CI.Width + Paired.Width) < 4;
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OptimizeListAgain |= CI.Width < 4;
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break;
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}
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case TBUFFER_LOAD: {
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MachineBasicBlock::iterator NewMI =
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mergeTBufferLoadPair(CI, Paired, InstsToMove);
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CI.setMI(NewMI, *this);
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OptimizeListAgain |= (CI.Width + Paired.Width) < 4;
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OptimizeListAgain |= CI.Width < 4;
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break;
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}
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case TBUFFER_STORE: {
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MachineBasicBlock::iterator NewMI =
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mergeTBufferStorePair(CI, Paired, InstsToMove);
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CI.setMI(NewMI, *this);
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OptimizeListAgain |= (CI.Width + Paired.Width) < 4;
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OptimizeListAgain |= CI.Width < 4;
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break;
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}
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}
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