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[X86] Add test case for missed opportunity to recognize a vXi1 shuffle as an insert into a zero vector. 

We are currently missing this because shuffle canonicalization
puts the zero vector as V1 and the subvector as V2. Our current
code doesn't recognize this case.

llvm-svn: 369225
This commit is contained in:
Craig Topper 2019-08-19 00:39:18 +00:00
parent 2ee46c7c4b
commit c9ee4c7c22
1 changed files with 18 additions and 0 deletions
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18
llvm/test/CodeGen/X86/avx512-skx-insert-subvec.ll
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@ -199,3 +199,21 @@ define <64 x i1> @test14(<2 x i1> %a) {
%res = shufflevector <2 x i1> %a, <2 x i1> zeroinitializer, <64 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
ret <64 x i1> %res
}
; Make sure we can recognize this shuffle as an insertion in to a zero vector.
define i8 @test15(<2 x i64> %x) {
; CHECK-LABEL: test15:
; CHECK: # %bb.0:
; CHECK-NEXT: vptestnmq %xmm0, %xmm0, %k0
; CHECK-NEXT: vpmovm2d %k0, %ymm0
; CHECK-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; CHECK-NEXT: vpmovd2m %ymm0, %k0
; CHECK-NEXT: kmovd %k0, %eax
; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%a = icmp eq <2 x i64> %x, zeroinitializer
%b = shufflevector <2 x i1> %a, <2 x i1> <i1 false, i1 undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
%c = bitcast <8 x i1> %b to i8
ret i8 %c
}