maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[X86] Add test for SDIV by sign bit (minsigned) value 

llvm-svn: 335671
This commit is contained in:
Simon Pilgrim 2018-06-26 22:03:00 +00:00
parent 6a94134b11
commit c9e60adcb5
1 changed files with 37 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
llvm/test/CodeGen/X86/combine-sdiv.ll
View File

@ -52,6 +52,43 @@ define <4 x i32> @combine_vec_sdiv_by_negone(<4 x i32> %x) {
ret <4 x i32> %1
}
; TODO fold (sdiv x, INT_MIN) -> select((icmp eq x, INT_MIN), 1, 0)
define i32 @combine_sdiv_by_minsigned(i32 %x) {
; CHECK-LABEL: combine_sdiv_by_minsigned:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: sarl $31, %eax
; CHECK-NEXT: shrl %eax
; CHECK-NEXT: leal (%rax,%rdi), %eax
; CHECK-NEXT: sarl $31, %eax
; CHECK-NEXT: retq
%1 = sdiv i32 %x, -2147483648
ret i32 %1
}
define <4 x i32> @combine_vec_sdiv_by_minsigned(<4 x i32> %x) {
; SSE-LABEL: combine_vec_sdiv_by_minsigned:
; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrad $31, %xmm1
; SSE-NEXT: psrld $1, %xmm1
; SSE-NEXT: paddd %xmm0, %xmm1
; SSE-NEXT: psrad $31, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_sdiv_by_minsigned:
; AVX: # %bb.0:
; AVX-NEXT: vpsrad $31, %xmm0, %xmm1
; AVX-NEXT: vpsrld $1, %xmm1, %xmm1
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrad $31, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = sdiv <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
ret <4 x i32> %1
}
; TODO fold (sdiv x, x) -> 1
define i32 @combine_sdiv_dupe(i32 %x) {
; CHECK-LABEL: combine_sdiv_dupe: