forked from OSchip/llvm-project
[AMDGPU/GlobalISel] Add llvm.amdgcn.fdiv.fast legalization.
Reviewers: arsenm Reviewed By: arsenm Subscribers: volkan, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64966 llvm-svn: 367344
This commit is contained in:
Austin Kerbow
parent
52b87ac32f
commit
c99f62e313
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@ -867,7 +867,8 @@ public:
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///
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/// \return a MachineInstrBuilder for the newly created instruction.
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MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
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const SrcOp &Op0, const SrcOp &Op1);
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const SrcOp &Op0, const SrcOp &Op1,
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Optional<unsigned> Flags = None);
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/// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
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///
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@ -880,7 +881,8 @@ public:
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///
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/// \return a MachineInstrBuilder for the newly created instruction.
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MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
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const SrcOp &Op0, const SrcOp &Op1);
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const SrcOp &Op0, const SrcOp &Op1,
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Optional<unsigned> Flags = None);
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/// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
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/// \p Elt, \p Idx
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@ -1210,6 +1212,12 @@ public:
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return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
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}
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MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
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const SrcOp &Src1,
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Optional<unsigned> Flags = None) {
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return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
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}
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MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
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const SrcOp &Src1,
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Optional<unsigned> Flags = None) {
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@ -1322,8 +1330,9 @@ public:
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}
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/// Build and insert \p Res = G_FABS \p Op0
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MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0) {
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return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0});
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MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
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Optional<unsigned> Flags = None) {
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return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
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}
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/// Build and insert \p Dst = G_FCANONICALIZE \p Src0
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@ -697,17 +697,19 @@ MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
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MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
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const DstOp &Res,
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const SrcOp &Op0,
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const SrcOp &Op1) {
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const SrcOp &Op1,
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Optional<unsigned> Flags) {
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return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1});
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return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
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}
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MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
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const SrcOp &Tst,
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const SrcOp &Op0,
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const SrcOp &Op1) {
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const SrcOp &Op1,
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Optional<unsigned> Flags) {
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return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1});
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return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
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}
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MachineInstrBuilder
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@ -1274,6 +1274,42 @@ bool AMDGPULegalizerInfo::legalizePreloadedArgIntrin(
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return false;
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}
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bool AMDGPULegalizerInfo::legalizeFDIVFast(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const {
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B.setInstr(MI);
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Register Res = MI.getOperand(0).getReg();
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Register LHS = MI.getOperand(2).getReg();
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Register RHS = MI.getOperand(3).getReg();
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uint16_t Flags = MI.getFlags();
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LLT S32 = LLT::scalar(32);
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LLT S1 = LLT::scalar(1);
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auto Abs = B.buildFAbs(S32, RHS, Flags);
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const APFloat C0Val(1.0f);
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auto C0 = B.buildConstant(S32, 0x6f800000);
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auto C1 = B.buildConstant(S32, 0x2f800000);
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auto C2 = B.buildConstant(S32, FloatToBits(1.0f));
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auto CmpRes = B.buildFCmp(CmpInst::FCMP_OGT, S1, Abs, C0, Flags);
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auto Sel = B.buildSelect(S32, CmpRes, C1, C2, Flags);
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auto Mul0 = B.buildFMul(S32, RHS, Sel, Flags);
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auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32}, false)
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.addUse(Mul0.getReg(0))
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.setMIFlags(Flags);
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auto Mul1 = B.buildFMul(S32, LHS, RCP, Flags);
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B.buildFMul(Res, Sel, Mul1, Flags);
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MI.eraseFromParent();
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return true;
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}
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bool AMDGPULegalizerInfo::legalizeImplicitArgPtr(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const {
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@ -1388,6 +1424,8 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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case Intrinsic::amdgcn_dispatch_id:
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return legalizePreloadedArgIntrin(MI, MRI, B,
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AMDGPUFunctionArgInfo::DISPATCH_ID);
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case Intrinsic::amdgcn_fdiv_fast:
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return legalizeFDIVFast(MI, MRI, B);
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default:
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return true;
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}
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@ -65,6 +65,9 @@ public:
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MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
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AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
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bool legalizeFDIVFast(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
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@ -1958,7 +1958,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case Intrinsic::amdgcn_udot4:
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case Intrinsic::amdgcn_sdot8:
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case Intrinsic::amdgcn_udot8:
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case Intrinsic::amdgcn_fdiv_fast:
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case Intrinsic::amdgcn_wwm:
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case Intrinsic::amdgcn_wqm:
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return getDefaultMappingVOP(MI);
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@ -0,0 +1,54 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: test_amdgcn_fdiv_fast
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_amdgcn_fdiv_fast
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY1]]
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1870659584
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 796917760
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216
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; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s32), [[C]]
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; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
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; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY1]], [[SELECT]]
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; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FMUL]](s32)
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; CHECK: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[INT]]
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; CHECK: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[SELECT]], [[FMUL1]]
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; CHECK: $vgpr0 = COPY [[FMUL2]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fdiv.fast), %0, %1
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$vgpr0 = COPY %2
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...
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---
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name: test_amdgcn_fdiv_fast_propagate_flags
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_amdgcn_fdiv_fast_propagate_flags
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: %3:_(s32) = nsz G_FABS [[COPY1]]
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1870659584
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 796917760
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216
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; CHECK: %7:_(s1) = nsz G_FCMP floatpred(ogt), %3(s32), [[C]]
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; CHECK: %8:_(s32) = nsz G_SELECT %7(s1), [[C1]], [[C2]]
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; CHECK: %9:_(s32) = nsz G_FMUL [[COPY1]], %8
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; CHECK: %10:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %9(s32)
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; CHECK: %11:_(s32) = nsz G_FMUL [[COPY]], %10
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; CHECK: %2:_(s32) = nsz G_FMUL %8, %11
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; CHECK: $vgpr0 = COPY %2(s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fdiv.fast), %0, %1
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$vgpr0 = COPY %2
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...
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