forked from OSchip/llvm-project
[Hexagon] Round 5 of selection pattern simplifications
Remove unnecessary type casts in patterns. llvm-svn: 286079
This commit is contained in:
Krzysztof Parzyszek
parent
f914278f8b
commit
c93815ef04
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@ -82,20 +82,20 @@ class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
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// since seteq/setgt/etc. are defined as ParFrags.
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class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
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: Pat<(VT (Op I32:$Rs, I32:$Rt)),
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(VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
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(MI IntRegs:$Rs, IntRegs:$Rt)>;
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def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
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def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
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def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
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def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
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def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
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def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
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def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
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def: Pat<(i32 (select I1:$Pu, I32:$Rs, I32:$Rt)),
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def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt),
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(C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
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def: Pat<(i32 (add I32:$Rs, s32_0ImmPred:$s16)),
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(i32 (A2_addi I32:$Rs, imm:$s16))>;
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def: Pat<(add I32:$Rs, s32_0ImmPred:$s16),
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(A2_addi I32:$Rs, imm:$s16)>;
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def: Pat<(or I32:$Rs, s32_0ImmPred:$s10),
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(A2_orir IntRegs:$Rs, imm:$s10)>;
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@ -112,13 +112,13 @@ def: Pat<(not I32:$src1),
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def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>;
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def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi imm:$s8)>;
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def : Pat<(i32 (select I1:$Pu, s32_0ImmPred:$s8, I32:$Rs)),
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def : Pat<(select I1:$Pu, s32_0ImmPred:$s8, I32:$Rs),
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(C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>;
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def : Pat<(i32 (select I1:$Pu, I32:$Rs, s32_0ImmPred:$s8)),
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def : Pat<(select I1:$Pu, I32:$Rs, s32_0ImmPred:$s8),
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(C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>;
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def : Pat<(i32 (select I1:$Pu, s32_0ImmPred:$s8, s8_0ImmPred:$S8)),
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def : Pat<(select I1:$Pu, s32_0ImmPred:$s8, s8_0ImmPred:$S8),
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(C2_muxii I1:$Pu, imm:$s8, imm:$S8)>;
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def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
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@ -164,33 +164,29 @@ def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
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// (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
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// is selected and the corresponding HexagonInst is passed in 'SwapInst'.
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multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
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multiclass T_MinMax_pats <PatFrag Op, PatLeaf Val,
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InstHexagon Inst, InstHexagon SwapInst> {
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def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
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(VT RC:$src1), (VT RC:$src2)),
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(Inst RC:$src1, RC:$src2)>;
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def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
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(VT RC:$src2), (VT RC:$src1)),
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(SwapInst RC:$src1, RC:$src2)>;
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def: Pat<(select (i1 (Op Val:$src1, Val:$src2)), Val:$src1, Val:$src2),
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(Inst Val:$src1, Val:$src2)>;
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def: Pat<(select (i1 (Op Val:$src1, Val:$src2)), Val:$src2, Val:$src1),
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(SwapInst Val:$src1, Val:$src2)>;
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}
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def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a), [{
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def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{
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return isPositiveHalfWord(N);
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}]>;
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multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
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defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
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defm: T_MinMax_pats<Op, I32, Inst, SwapInst>;
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def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
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(i32 PositiveHalfWord:$src2))),
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(i32 PositiveHalfWord:$src1),
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(i32 PositiveHalfWord:$src2))), i16),
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def: Pat<(sext_inreg (select (i1 (Op IsPosHalf:$src1, IsPosHalf:$src2)),
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IsPosHalf:$src1, IsPosHalf:$src2),
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i16),
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(Inst IntRegs:$src1, IntRegs:$src2)>;
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def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
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(i32 PositiveHalfWord:$src2))),
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(i32 PositiveHalfWord:$src2),
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(i32 PositiveHalfWord:$src1))), i16),
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def: Pat<(sext_inreg (select (i1 (Op IsPosHalf:$src1, IsPosHalf:$src2)),
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IsPosHalf:$src2, IsPosHalf:$src1),
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i16),
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(SwapInst IntRegs:$src1, IntRegs:$src2)>;
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}
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@ -222,8 +218,7 @@ def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
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def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
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def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
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def: Pat<(i1 (not I1:$Ps)),
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(C2_not PredRegs:$Ps)>;
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def: Pat<(i1 (not I1:$Ps)), (C2_not PredRegs:$Ps)>;
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def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>;
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def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>;
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@ -235,17 +230,12 @@ def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
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def: Pat<(br bb:$dst),
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(J2_jump brtarget:$dst)>;
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def: Pat<(retflag),
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(PS_jmpret (i32 R31))>;
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def: Pat<(brcond I1:$src1, bb:$offset),
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(J2_jumpt PredRegs:$src1, bb:$offset)>;
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def: Pat<(br bb:$dst), (J2_jump brtarget:$dst)>;
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def: Pat<(brcond I1:$src1, bb:$block), (J2_jumpt PredRegs:$src1, bb:$block)>;
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def: Pat<(brind I32:$dst), (J2_jumpr IntRegs:$dst)>;
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def: Pat<(eh_return),
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(EH_RETURN_JMPR (i32 R31))>;
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def: Pat<(brind I32:$dst),
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(J2_jumpr IntRegs:$dst)>;
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def: Pat<(retflag), (PS_jmpret (i32 R31))>;
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def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>;
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// Patterns to select load-indexed (i.e. load from base+offset).
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multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
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@ -330,9 +320,8 @@ def: T_MType_acc_pat2 <M4_and_or, or, and>;
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def: T_MType_acc_pat2 <M4_xor_or, or, xor>;
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class T_MType_acc_pat3 <InstHexagon MI, SDNode firstOp, SDNode secOp>
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: Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2,
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(not IntRegs:$src3)))),
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(i32 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3))>;
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: Pat <(secOp I32:$src1, (firstOp I32:$src2, (not I32:$src3))),
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(MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def: T_MType_acc_pat3 <M4_or_andn, and, or>;
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def: T_MType_acc_pat3 <M4_and_andn, and, and>;
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@ -351,46 +340,34 @@ def Sext64Ld : PatLeaf<(i64 DoubleRegs:$src1), [{
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LD->getMemoryVT().getScalarType() == MVT::i32;
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}]>;
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def: Pat<(i64 (mul (Aext64 I32:$src1), (Aext64 I32:$src2))),
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def: Pat<(mul (Aext64 I32:$src1), (Aext64 I32:$src2)),
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(M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
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def: Pat<(i64 (mul (Sext64 I32:$src1), (Sext64 I32:$src2))),
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def: Pat<(mul (Sext64 I32:$src1), (Sext64 I32:$src2)),
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(M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
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def: Pat<(i64 (mul Sext64Ld:$src1, Sext64Ld:$src2)),
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def: Pat<(mul Sext64Ld:$src1, Sext64Ld:$src2),
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(M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
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// Multiply and accumulate, use full result.
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// Rxx[+-]=mpy(Rs,Rt)
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def: Pat<(i64 (add I64:$src1,
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(mul (Sext64 I32:$src2),
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(Sext64 I32:$src3)))),
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def: Pat<(add I64:$src1, (mul (Sext64 I32:$src2), (Sext64 I32:$src3))),
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(M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def: Pat<(i64 (sub I64:$src1,
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(mul (Sext64 I32:$src2),
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(Sext64 I32:$src3)))),
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def: Pat<(sub I64:$src1, (mul (Sext64 I32:$src2), (Sext64 I32:$src3))),
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(M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def: Pat<(i64 (add I64:$src1,
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(mul (Aext64 I32:$src2),
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(Aext64 I32:$src3)))),
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def: Pat<(add I64:$src1, (mul (Aext64 I32:$src2), (Aext64 I32:$src3))),
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(M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def: Pat<(i64 (add I64:$src1,
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(mul (Zext64 I32:$src2),
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(Zext64 I32:$src3)))),
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def: Pat<(add I64:$src1, (mul (Zext64 I32:$src2), (Zext64 I32:$src3))),
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(M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def: Pat<(i64 (sub I64:$src1,
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(mul (Aext64 I32:$src2),
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(Aext64 I32:$src3)))),
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def: Pat<(sub I64:$src1, (mul (Aext64 I32:$src2), (Aext64 I32:$src3))),
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(M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def: Pat<(i64 (sub I64:$src1,
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(mul (Zext64 I32:$src2),
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(Zext64 I32:$src3)))),
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def: Pat<(sub I64:$src1, (mul (Zext64 I32:$src2), (Zext64 I32:$src3))),
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(M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset,
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@ -515,15 +492,13 @@ def: Storexm_simple_pat<truncstorei32, I64, LoReg, S2_storeri_io>;
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def: Pat <(Sext64 I32:$src), (A2_sxtw I32:$src)>;
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def: Pat<(i32 (select (i1 (setlt I32:$src, 0)),
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(i32 (sub 0, I32:$src)),
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I32:$src)),
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def: Pat<(select (i1 (setlt I32:$src, 0)), (sub 0, I32:$src), I32:$src),
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(A2_abs IntRegs:$src)>;
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let AddedComplexity = 50 in
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def: Pat<(i32 (xor (add (sra I32:$src, (i32 31)),
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I32:$src),
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(sra I32:$src, (i32 31)))),
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def: Pat<(xor (add (sra I32:$src, (i32 31)),
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I32:$src),
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(sra I32:$src, (i32 31))),
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(A2_abs IntRegs:$src)>;
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def: Pat<(sra I32:$src, u5_0ImmPred:$u5),
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@ -533,27 +508,25 @@ def: Pat<(srl I32:$src, u5_0ImmPred:$u5),
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def: Pat<(shl I32:$src, u5_0ImmPred:$u5),
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(S2_asl_i_r IntRegs:$src, imm:$u5)>;
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def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5_0ImmPred:$src2)),
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(i32 1))),
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(i32 1))),
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def: Pat<(sra (add (sra I32:$src1, u5_0ImmPred:$src2), 1), (i32 1)),
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(S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred:$src2)>;
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def : Pat<(not I64:$src1),
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(A2_notp DoubleRegs:$src1)>;
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// Count leading zeros.
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def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
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def: Pat<(ctlz I32:$Rs), (S2_cl0 I32:$Rs)>;
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def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
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// Count trailing zeros: 32-bit.
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def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
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def: Pat<(cttz I32:$Rs), (S2_ct0 I32:$Rs)>;
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// Count leading ones.
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def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
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def: Pat<(ctlz (not I32:$Rs)), (S2_cl1 I32:$Rs)>;
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def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
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// Count trailing ones: 32-bit.
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def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
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def: Pat<(cttz (not I32:$Rs)), (S2_ct1 I32:$Rs)>;
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def: Pat<(i32 (and I32:$Rs, (not (shl 1, u5_0ImmPred:$u5)))),
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(S2_clrbit_i IntRegs:$Rs, u5_0ImmPred:$u5)>;
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@ -1082,7 +1055,7 @@ def: Pat<(mul I32:$src1, (ineg n8_0ImmPred:$src2)),
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(M2_mpysin IntRegs:$src1, u8_0ImmPred:$src2)>;
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multiclass MinMax_pats_p<PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
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defm: T_MinMax_pats<Op, DoubleRegs, i64, Inst, SwapInst>;
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defm: T_MinMax_pats<Op, I64, Inst, SwapInst>;
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}
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def: Pat<(add (Sext64 I32:$Rs), I64:$Rt),
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@ -1958,8 +1931,7 @@ def u7_0PosImmPred : ImmLeaf<i32, [{
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// retval = (c-48) < 10 ? 1 : 0;
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let AddedComplexity = 139 in
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def: Pat<(i32 (zext (i1 (setult (i32 (and I32:$src1, 255)),
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u7_0PosImmPred:$src2)))),
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def: Pat<(i32 (zext (i1 (setult (and I32:$src1, 255), u7_0PosImmPred:$src2)))),
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(C2_muxii (A4_cmpbgtui IntRegs:$src1, (UDEC1 imm:$src2)), 0, 1)>;
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class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
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@ -2031,7 +2003,6 @@ def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>;
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def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
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def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
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// Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
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def: Loadam_pat<load, i1, addrga, I32toI1, PS_loadrubabs>;
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def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>;
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@ -2157,11 +2128,9 @@ def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, PS_storerhabs>;
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def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, PS_storeriabs>;
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def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, PS_storerdabs>;
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def: Pat<(or (or (or (shl (i64 (zext (i32 (and I32:$b, (i32 65535))))),
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(i32 16)),
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def: Pat<(or (or (or (shl (i64 (zext (and I32:$b, (i32 65535)))), (i32 16)),
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(i64 (zext (i32 (and I32:$a, (i32 65535)))))),
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(shl (i64 (anyext (i32 (and I32:$c, (i32 65535))))),
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(i32 32))),
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(shl (i64 (anyext (and I32:$c, (i32 65535)))), (i32 32))),
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(shl (Aext64 I32:$d), (i32 48))),
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(Insert4 IntRegs:$a, IntRegs:$b, IntRegs:$c, IntRegs:$d)>;
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@ -2187,12 +2156,11 @@ def ftoi : SDNodeXForm<fpimm, [{
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}]>;
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def: Pat<(sra (i64 (add (i64 (sra I64:$src1, u6_0ImmPred:$src2)), 1)), (i32 1)),
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def: Pat<(sra (i64 (add (sra I64:$src1, u6_0ImmPred:$src2), 1)), (i32 1)),
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(S2_asr_i_p_rnd I64:$src1, imm:$src2)>;
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def SDTHexagonI32I64: SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
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SDTCisVT<1, i64>]>;
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def HexagonPOPCOUNT: SDNode<"HexagonISD::POPCOUNT", SDTHexagonI32I64>;
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def: Pat<(HexagonPOPCOUNT I64:$Rss), (S5_popcountp I64:$Rss)>;
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