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Fix a small thinko for constant i64 lock/orq optimization where we 

we didn't have an opcode for 64-bit constant or expressions.

Fixes rdar://9692967

llvm-svn: 134121
This commit is contained in:
Eric Christopher 2011-06-30 00:48:30 +00:00
parent 8bdae58c3a
commit c932173773
2 changed files with 22 additions and 2 deletions
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6
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -1612,16 +1612,18 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
Opc = AtomicOpcTbl[Op][I32]; Opc = AtomicOpcTbl[Op][I32];
break; break;
case MVT::i64: case MVT::i64:
Opc = AtomicOpcTbl[Op][I64];
if (isCN) { if (isCN) {
if (immSext8(Val.getNode())) if (immSext8(Val.getNode()))
Opc = AtomicOpcTbl[Op][SextConstantI64]; Opc = AtomicOpcTbl[Op][SextConstantI64];
else if (i64immSExt32(Val.getNode())) else if (i64immSExt32(Val.getNode()))
Opc = AtomicOpcTbl[Op][ConstantI64]; Opc = AtomicOpcTbl[Op][ConstantI64];
} else }
Opc = AtomicOpcTbl[Op][I64];
break; break;
} }
assert(Opc != 0 && "Invalid arith lock transform!");
DebugLoc dl = Node->getDebugLoc(); DebugLoc dl = Node->getDebugLoc();
SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
dl, NVT), 0); dl, NVT), 0);

18
llvm/test/CodeGen/X86/atomic-or.ll Normal file
View File

@ -0,0 +1,18 @@
; RUN: llc < %s -march=x86-64 | FileCheck %s
; rdar://9692967
define void @do_the_sync(i64* %p, i32 %b) nounwind {
entry:
%p.addr = alloca i64*, align 8
store i64* %p, i64** %p.addr, align 8
%tmp = load i64** %p.addr, align 8
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
; CHECK: lock
; CHECK-NEXT: orq $2147483648
%0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483648)
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
ret void
}
declare i64 @llvm.atomic.load.or.i64.p0i64(i64* nocapture, i64) nounwind
declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind