forked from OSchip/llvm-project
Remove the MCR asm parser hack and start using the custom target specific asm
parsing of operands introduced in r125030. As a small note, besides using a more generic approach we can also have more descriptive output when debugging llvm-mc, example: mcr p7, #1, r5, c1, c1, #4 note: parsed instruction: ['mcr', <ARMCC::al>, <coprocessor number: 7>, 1, <register 73>, <coprocessor register: 1>, <coprocessor register: 1>, 4] llvm-svn: 125052
This commit is contained in:
Bruno Cardoso Lopes
parent
05a975d777
commit
c9253b4deb
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@ -588,12 +588,26 @@ def nohash_imm : Operand<i32> {
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let PrintMethod = "printNoHashImmediate";
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}
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def CoprocNumAsmOperand : AsmOperandClass {
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let Name = "CoprocNum";
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let SuperClasses = [];
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let ParserMethod = "ParseCoprocNumOperand";
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}
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def CoprocRegAsmOperand : AsmOperandClass {
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let Name = "CoprocReg";
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let SuperClasses = [];
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let ParserMethod = "ParseCoprocRegOperand";
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}
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def p_imm : Operand<i32> {
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let PrintMethod = "printPImmediate";
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let ParserMatchClass = CoprocNumAsmOperand;
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}
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def c_imm : Operand<i32> {
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let PrintMethod = "printCImmediate";
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let ParserMatchClass = CoprocRegAsmOperand;
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}
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//===----------------------------------------------------------------------===//
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@ -54,11 +54,12 @@ class ARMAsmParser : public TargetAsmParser {
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int TryParseRegister();
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virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
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bool TryParseCoprocessorOperandName(SmallVectorImpl<MCParsedAsmOperand*>&);
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bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*>&);
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bool ParseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*>&);
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bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, bool hasCoprocOp);
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bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
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bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
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const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
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MCSymbolRefExpr::VariantKind Variant);
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@ -115,6 +116,8 @@ class ARMOperand : public MCParsedAsmOperand {
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enum KindTy {
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CondCode,
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CCOut,
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CoprocNum,
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CoprocReg,
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Immediate,
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Memory,
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Register,
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@ -132,6 +135,10 @@ class ARMOperand : public MCParsedAsmOperand {
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ARMCC::CondCodes Val;
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} CC;
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struct {
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unsigned Val;
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} Cop;
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struct {
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const char *Data;
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unsigned Length;
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@ -185,6 +192,10 @@ public:
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case SPRRegisterList:
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Registers = o.Registers;
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break;
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case CoprocNum:
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case CoprocReg:
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Cop = o.Cop;
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break;
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case Immediate:
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Imm = o.Imm;
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break;
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@ -204,6 +215,11 @@ public:
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return CC.Val;
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}
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unsigned getCoproc() const {
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assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
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return Cop.Val;
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}
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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@ -259,6 +275,8 @@ public:
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/// @}
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bool isCoprocNum() const { return Kind == CoprocNum; }
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bool isCoprocReg() const { return Kind == CoprocReg; }
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bool isCondCode() const { return Kind == CondCode; }
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bool isCCOut() const { return Kind == CCOut; }
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bool isImm() const { return Kind == Immediate; }
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@ -314,6 +332,16 @@ public:
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Inst.addOperand(MCOperand::CreateReg(RegNum));
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}
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void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateImm(getCoproc()));
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}
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void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateImm(getCoproc()));
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}
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void addCCOutOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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@ -391,6 +419,22 @@ public:
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return Op;
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}
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static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
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ARMOperand *Op = new ARMOperand(CoprocNum);
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Op->Cop.Val = CopVal;
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
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ARMOperand *Op = new ARMOperand(CoprocReg);
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Op->Cop.Val = CopVal;
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
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ARMOperand *Op = new ARMOperand(CCOut);
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Op->Reg.RegNum = RegNum;
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@ -492,6 +536,12 @@ void ARMOperand::dump(raw_ostream &OS) const {
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case CCOut:
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OS << "<ccout " << getReg() << ">";
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break;
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case CoprocNum:
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OS << "<coprocessor number: " << getCoproc() << ">";
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break;
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case CoprocReg:
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OS << "<coprocessor register: " << getCoproc() << ">";
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break;
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case Immediate:
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getImm()->print(OS);
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break;
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@ -609,13 +659,16 @@ TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return false;
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}
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static int MatchCoprocessorOperandName(StringRef Name) {
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/// MatchCoprocessorOperandName - Try to parse an coprocessor related
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/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
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/// "c5", ...
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static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
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// Use the same layout as the tablegen'erated register name matcher. Ugly,
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// but efficient.
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switch (Name.size()) {
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default: break;
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case 2:
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if (Name[0] != 'p' && Name[0] != 'c')
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if (Name[0] != CoprocOp)
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return -1;
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switch (Name[1]) {
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default: return -1;
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@ -632,7 +685,7 @@ static int MatchCoprocessorOperandName(StringRef Name) {
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}
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break;
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case 3:
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if ((Name[0] != 'p' && Name[0] != 'c') || Name[1] != '1')
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if (Name[0] != CoprocOp || Name[1] != '1')
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return -1;
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switch (Name[2]) {
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default: return -1;
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@ -650,24 +703,39 @@ static int MatchCoprocessorOperandName(StringRef Name) {
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return -1;
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}
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/// TryParseCoprocessorOperandName - Try to parse an coprocessor related
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/// instruction with a symbolic operand name. The token must be an Identifier
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/// when called, and if it is a coprocessor related operand name, the token is
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/// eaten and the operand is added to the operand list. Example: operands like
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/// "p1", "p7", "c3", "c5", ...
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/// ParseCoprocNumOperand - Try to parse an coprocessor number operand. The
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/// token must be an Identifier when called, and if it is a coprocessor
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/// number, the token is eaten and the operand is added to the operand list.
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bool ARMAsmParser::
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TryParseCoprocessorOperandName(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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ParseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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const AsmToken &Tok = Parser.getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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int Num = MatchCoprocessorOperandName(Tok.getString());
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int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
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if (Num == -1)
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return true;
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Parser.Lex(); // Eat identifier token.
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Operands.push_back(ARMOperand::CreateImm(
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MCConstantExpr::Create(Num, getContext()), S, Parser.getTok().getLoc()));
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Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
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return false;
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}
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/// ParseCoprocRegOperand - Try to parse an coprocessor register operand. The
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/// token must be an Identifier when called, and if it is a coprocessor
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/// number, the token is eaten and the operand is added to the operand list.
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bool ARMAsmParser::
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ParseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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const AsmToken &Tok = Parser.getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
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if (Reg == -1)
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return true;
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Parser.Lex(); // Eat identifier token.
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Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
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return false;
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}
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@ -974,8 +1042,15 @@ bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
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/// Parse a arm instruction operand. For now this parses the operand regardless
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/// of the mnemonic.
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bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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bool hasCoprocOp){
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StringRef Mnemonic) {
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SMLoc S, E;
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// Check if the current operand has a custom associated parser, if so, try to
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// custom parse the operand, or fallback to the general approach.
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MatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
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if (ResTy == Match_Success)
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return false;
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switch (getLexer().getKind()) {
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default:
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Error(Parser.getTok().getLoc(), "unexpected token in operand");
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@ -983,8 +1058,6 @@ bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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case AsmToken::Identifier:
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if (!TryParseRegisterWithWriteBack(Operands))
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return false;
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if (hasCoprocOp && !TryParseCoprocessorOperandName(Operands))
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return false;
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// Fall though for the Identifier case that is not a register or a
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// special name.
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@ -1273,22 +1346,10 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
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Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
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}
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// Enable the parsing of instructions containing coprocessor related
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// asm syntax, such as coprocessor names "p7, p15, ..." and coprocessor
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// registers "c1, c3, ..."
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// FIXME: we probably want AsmOperandClass and ParserMatchClass declarations
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// in the .td file rather than hacking the ASMParser for every symbolic
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// operand type.
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bool hasCoprocOp = (Head == "mcr" || Head == "mcr2" ||
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Head == "mcrr" || Head == "mcrr2" ||
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Head == "mrc" || Head == "mrc2" ||
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Head == "mrrc" || Head == "mrrc2" ||
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Head == "cdp" || Head == "cdp2");
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// Read the remaining operands.
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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// Read the first operand.
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if (ParseOperand(Operands, hasCoprocOp)) {
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if (ParseOperand(Operands, Head)) {
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Parser.EatToEndOfStatement();
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return true;
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}
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@ -1297,7 +1358,7 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
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Parser.Lex(); // Eat the comma.
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// Parse and remember the operand.
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if (ParseOperand(Operands, hasCoprocOp)) {
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if (ParseOperand(Operands, Head)) {
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Parser.EatToEndOfStatement();
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return true;
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}
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