forked from OSchip/llvm-project
[X86] Give VINSERTPS the same intinerary as INSERTPS.
llvm-svn: 328954
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@ -5806,7 +5806,7 @@ let Constraints = "$src1 = $dst" in
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// vector. The next one matches the intrinsic and could zero arbitrary elements
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// in the target vector.
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multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
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OpndItins itins = DEFAULT_ITINS> {
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OpndItins itins = SSE_INSERT_ITINS> {
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def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, u8imm:$src3),
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!if(Is2Addr,
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@ -5831,9 +5831,10 @@ multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
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let ExeDomain = SSEPackedSingle in {
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let Predicates = [UseAVX] in
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defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V, VEX_WIG;
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defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>,
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VEX_4V, VEX_WIG;
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let Constraints = "$src1 = $dst" in
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defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
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defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1>;
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}
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let Predicates = [UseAVX] in {
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