forked from OSchip/llvm-project
[PPC] Generate positive FP zero using xor insn instead of loading from constant area
https://reviews.llvm.org/D23614 Currently we load +0.0 from constant area. That can change to be generated using XOR instruction. llvm-svn: 284995
This commit is contained in:
Ehsan Amiri
parent
47f2616b6a
commit
c90b02cf50
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@ -562,6 +562,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
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if (Subtarget.hasP8Altivec())
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
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if (Subtarget.hasVSX())
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
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// Altivec does not contain unordered floating-point compare instructions
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setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
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@ -12367,3 +12371,20 @@ void PPCTargetLowering::insertSSPDeclarations(Module &M) const {
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if (!Subtarget.isTargetLinux())
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return TargetLowering::insertSSPDeclarations(M);
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}
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bool PPCTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
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if (!VT.isSimple() || !Subtarget.hasVSX())
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return false;
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switch(VT.getSimpleVT().SimpleTy) {
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default:
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// For FP types that are currently not supported by PPC backend, return
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// false. Examples: f16, f80.
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return false;
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case MVT::f32:
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case MVT::f64:
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case MVT::ppcf128:
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return Imm.isPosZero();
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}
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}
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@ -769,6 +769,7 @@ namespace llvm {
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bool useLoadStackGuardNode() const override;
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void insertSSPDeclarations(Module &M) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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private:
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struct ReuseLoadInfo {
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SDValue Ptr;
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@ -1076,6 +1076,13 @@ class XX3Form_Zero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
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let XB = XT;
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}
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class XX3Form_SetZero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
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let XB = XT;
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let XA = XT;
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}
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class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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@ -621,6 +621,9 @@ def s17imm : Operand<i32> {
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let ParserMatchClass = PPCS17ImmAsmOperand;
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let DecoderMethod = "decodeSImmOperand<16>";
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}
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def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
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def PPCDirectBrAsmOperand : AsmOperandClass {
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let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
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let RenderMethod = "addBranchTargetOperands";
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@ -791,6 +791,17 @@ let Uses = [RM] in {
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"xxlxor $XT, $XT, $XT", IIC_VecGeneral,
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[(set v4i32:$XT, (v4i32 immAllZerosV))]>;
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let isCodeGenOnly = 1 in {
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def XXLXORdpz : XX3Form_SetZero<60, 154,
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(outs vsfrc:$XT), (ins),
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"xxlxor $XT, $XT, $XT", IIC_VecGeneral,
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[(set f64:$XT, (fpimm0))]>;
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def XXLXORspz : XX3Form_SetZero<60, 154,
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(outs vssrc:$XT), (ins),
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"xxlxor $XT, $XT, $XT", IIC_VecGeneral,
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[(set f32:$XT, (fpimm0))]>;
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}
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// Permutation Instructions
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def XXMRGHW : XX3Form<60, 18,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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@ -0,0 +1,71 @@
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; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mattr=+vsx < %s | \
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; RUN: FileCheck %s --implicit-check-not lxvd2x --implicit-check-not lfs
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; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mattr=-vsx -mattr=-p8altivec < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-NVSXP8A --implicit-check-not xxlxor \
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; RUN: --implicit-check-not vxor
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define signext i32 @t1(float %x) local_unnamed_addr #0 {
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entry:
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%cmp = fcmp ogt float %x, 0.000000e+00
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%tmp = select i1 %cmp, i32 43, i32 11
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ret i32 %tmp
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; CHECK-LABEL: t1:
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; CHECK: xxlxor [[REG1:[0-9]+]], [[REG1]], [[REG1]]
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; CHECK: fcmpu {{[0-9]+}}, {{[0-9]+}}, [[REG1]]
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; CHECK: blr
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; CHECK-NVSXP8A: lfs [[REG1:[0-9]+]]
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; CHECK-NVSXP8A: fcmpu {{[0-9]+}}, {{[0-9]+}}, [[REG1]]
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; CHECK-NVSXP8A: blr
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}
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define signext i32 @t2(double %x) local_unnamed_addr #0 {
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entry:
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%cmp = fcmp ogt double %x, 0.000000e+00
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%tmp = select i1 %cmp, i32 43, i32 11
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ret i32 %tmp
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; CHECK-LABEL: t2:
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; CHECK: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
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; CHECK: xscmpudp {{[0-9]+}}, {{[0-9]+}}, [[REG2]]
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; CHECK: blr
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; CHECK-NVSXP8A: lfs [[REG2:[0-9]+]]
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; CHECK-NVSXP8A: fcmpu {{[0-9]+}}, {{[0-9]+}}, [[REG2]]
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; CHECK-NVSXP8A: blr
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}
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define signext i32 @t3(ppc_fp128 %x) local_unnamed_addr #0 {
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entry:
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%cmp = fcmp ogt ppc_fp128 %x, 0xM00000000000000000000000000000000
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%tmp = select i1 %cmp, i32 43, i32 11
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ret i32 %tmp
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; CHECK-LABEL: t3:
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; CHECK: xxlxor [[REG3:[0-9]+]], [[REG3]], [[REG3]]
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; CHECK: fcmpu {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
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; CHECK: fcmpu {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
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; CHECK: blr
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; CHECK-NVSXP8A: lfs [[REG3:[0-9]+]]
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; CHECK-NVSXP8A: fcmpu {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
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; CHECK-NVSXP8A: blr
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}
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define <2 x double> @t4() local_unnamed_addr #0 {
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ret <2 x double> zeroinitializer
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; CHECK-LABEL: t4:
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; CHECK: vxor [[REG4:[0-9]+]], [[REG4]], [[REG4]]
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; CHECK: blr
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; CHECK-NVSXP8A: lfs [[REG4:[0-9]+]]
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; CHECK-NVSXP8A: fmr {{[0-9]+}}, [[REG4:[0-9]+]]
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; CHECK-NVSXP8A: blr
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}
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define <2 x i64> @t5() local_unnamed_addr #0 {
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ret <2 x i64> zeroinitializer
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; CHECK-LABEL: t5:
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; CHECK: vxor [[REG5:[0-9]+]], [[REG5]], [[REG5]]
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; CHECK: blr
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; CHECK-NVSXP8A: lvx
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; CHECK-NVSXP8A: blr
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}
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@ -13,7 +13,7 @@ entry:
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; CHECK-LABEL: @test1
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; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
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; CHECK-DAG: li [[REG1:[0-9]+]], 1
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; CHECK-DAG: lfs [[REG2:[0-9]+]],
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; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
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; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
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; CHECK: crnor
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; CHECK: crnor
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@ -33,7 +33,7 @@ entry:
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; CHECK-LABEL: @test2
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; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
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; CHECK-DAG: li [[REG1:[0-9]+]], 1
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; CHECK-DAG: lfs [[REG2:[0-9]+]],
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; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
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; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
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; CHECK: crnor
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; CHECK: crnor
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@ -55,7 +55,7 @@ entry:
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; CHECK-LABEL: @test3
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; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
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; CHECK-DAG: li [[REG1:[0-9]+]], 1
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; CHECK-DAG: lfs [[REG2:[0-9]+]],
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; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
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; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
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; CHECK: crnor
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; CHECK: crnor
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@ -2,7 +2,7 @@
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define i1 @TestULT(double %t0) {
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; CHECK-LABEL: TestULT:
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; CHECK: mcrf
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; CHECK: xscmpudp
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; CHECK: blr
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entry:
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%t1 = fcmp ult double %t0, 0.000000e+00
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@ -49,7 +49,7 @@ good:
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define i1 @TestUEQ(double %t0) {
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; CHECK-LABEL: TestUEQ:
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; CHECK: mcrf
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; CHECK: xscmpudp
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; CHECK: blr
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entry:
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%t1 = fcmp ueq double %t0, 0.000000e+00
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@ -64,7 +64,7 @@ good:
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define i1 @TestUGT(double %t0) {
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; CHECK-LABEL: TestUGT:
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; CHECK: mcrf
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; CHECK: xscmpudp
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; CHECK: blr
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entry:
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%t1 = fcmp ugt double %t0, 0.000000e+00
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@ -111,7 +111,7 @@ good:
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define i1 @TestOLE(double %t0) {
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; CHECK-LABEL: TestOLE:
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; CHECK: mcrf
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; CHECK: xscmpudp
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; CHECK: blr
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entry:
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%t1 = fcmp ole double %t0, 0.000000e+00
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@ -126,7 +126,7 @@ good:
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define i1 @TestONE(double %t0) {
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; CHECK-LABEL: TestONE:
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; CHECK: mcrf
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; CHECK: xscmpudp
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; CHECK: blr
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entry:
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%t1 = fcmp one double %t0, 0.000000e+00
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@ -173,7 +173,7 @@ good:
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define i1 @TestOGE(double %t0) {
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; CHECK-LABEL: TestOGE:
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; CHECK: mcrf
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; CHECK: xscmpudp
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; CHECK: blr
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entry:
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%t1 = fcmp oge double %t0, 0.000000e+00
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@ -5,7 +5,7 @@ target triple = "powerpc64le-unknown-linux-gnu"
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; Check that the conditional return block of fmax_double3.exit was not
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; duplicated into the if.then.i block
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; CHECK: # %if.then.i
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; CHECK: lxvd2x
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; CHECK: xxlxor
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; CHECK: stxvd2x
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; CHECK-NOT: bclr
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; CHECK: {{^}}.LBB{{[0-9_]+}}:
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