forked from OSchip/llvm-project
Fix a number of Clang-Tidy warnings.
PiperOrigin-RevId: 270632324
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f1442f1eff
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c900d4994e
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@ -56,7 +56,7 @@ std::pair<mlir::Value *, unsigned> linalg::getViewRootIndexing(Value *view,
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unsigned sliceDim = sliceOp.getSlicingDim();
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auto *indexing = sliceOp.getIndexing();
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if (indexing->getDefiningOp()) {
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if (auto rangeOp = cast<RangeOp>(indexing->getDefiningOp())) {
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if (auto rangeOp = dyn_cast<RangeOp>(indexing->getDefiningOp())) {
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// If I sliced with a range and I sliced at this dim, then I'm it.
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if (dim == sliceDim) {
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return std::make_pair(rangeOp.getResult(), dim);
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@ -258,7 +258,7 @@ struct Rewriter : public OpRewritePattern<LoadOrStoreOpTy> {
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struct LowerLinalgLoadStorePass
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: public FunctionPass<LowerLinalgLoadStorePass> {
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void runOnFunction() {
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void runOnFunction() override {
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OwningRewritePatternList patterns;
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auto *context = &getContext();
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patterns.insert<Rewriter<linalg::LoadOp>, Rewriter<linalg::StoreOp>>(
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@ -2632,7 +2632,7 @@ void FlatAffineConstraints::FourierMotzkinEliminate(
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LLVM_DEBUG(llvm::dbgs() << "FM isResultIntegerExact: " << (lcmProducts == 1)
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<< "\n");
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if (lcmProducts == 1 && isResultIntegerExact)
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*isResultIntegerExact = 1;
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*isResultIntegerExact = true;
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// Copy over the constraints not involving this variable.
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for (auto nbPos : nbIndices) {
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@ -249,7 +249,7 @@ class ReturnToSPIRVConversion : public ConversionPattern {
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public:
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ReturnToSPIRVConversion(MLIRContext *context)
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: ConversionPattern(ReturnOp::getOperationName(), 1, context) {}
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virtual PatternMatchResult
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PatternMatchResult
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matchAndRewrite(Operation *op, ArrayRef<Value *> operands,
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ConversionPatternRewriter &rewriter) const override {
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if (op->getNumOperands()) {
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@ -164,7 +164,7 @@ void mlir::populateVectorToLLVMConversionPatterns(
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namespace {
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struct LowerVectorToLLVMPass : public ModulePass<LowerVectorToLLVMPass> {
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void runOnModule();
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void runOnModule() override;
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};
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} // namespace
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@ -121,7 +121,7 @@ struct UniformDequantizePattern : public OpRewritePattern<DequantizeCastOp> {
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using OpRewritePattern<DequantizeCastOp>::OpRewritePattern;
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PatternMatchResult matchAndRewrite(DequantizeCastOp op,
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PatternRewriter &rewriter) const {
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PatternRewriter &rewriter) const override {
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Type inputType = op.arg()->getType();
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Type outputType = op.getResult()->getType();
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@ -322,7 +322,7 @@ struct UniformRealAddEwPattern : public OpRewritePattern<RealAddEwOp> {
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using OpRewritePattern<RealAddEwOp>::OpRewritePattern;
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PatternMatchResult matchAndRewrite(RealAddEwOp op,
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PatternRewriter &rewriter) const {
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PatternRewriter &rewriter) const override {
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const UniformBinaryOpInfo info(op, op.lhs(), op.rhs(), op.clamp_min(),
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op.clamp_max());
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if (!info.isValid()) {
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@ -342,7 +342,7 @@ struct UniformRealMulEwPattern : public OpRewritePattern<RealMulEwOp> {
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using OpRewritePattern<RealMulEwOp>::OpRewritePattern;
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PatternMatchResult matchAndRewrite(RealMulEwOp op,
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PatternRewriter &rewriter) const {
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PatternRewriter &rewriter) const override {
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const UniformBinaryOpInfo info(op, op.lhs(), op.rhs(), op.clamp_min(),
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op.clamp_max());
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if (!info.isValid()) {
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@ -337,7 +337,7 @@ struct LinalgFusionPass : public FunctionPass<LinalgFusionPass> {
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LinalgFusionPass() = default;
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LinalgFusionPass(ArrayRef<int64_t> sizes);
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void runOnFunction() { fuseLinalgOps(getFunction(), tileSizes); }
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void runOnFunction() override { fuseLinalgOps(getFunction(), tileSizes); }
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SmallVector<int64_t, 8> tileSizes;
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};
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@ -854,7 +854,7 @@ populateLinalgToLLVMConversionPatterns(LinalgTypeConverter &converter,
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namespace {
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struct LowerLinalgToLLVMPass : public ModulePass<LowerLinalgToLLVMPass> {
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void runOnModule();
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void runOnModule() override;
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};
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} // namespace
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@ -373,7 +373,7 @@ populateLinalgToLoopRewritePatterns(OwningRewritePatternList &patterns,
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namespace {
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struct LowerLinalgToLoopsPass : public FunctionPass<LowerLinalgToLoopsPass> {
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void runOnFunction();
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void runOnFunction() override;
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};
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} // namespace
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@ -513,7 +513,7 @@ struct LinalgTilingPass : public FunctionPass<LinalgTilingPass> {
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LinalgTilingPass() = default;
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LinalgTilingPass(ArrayRef<int64_t> sizes, bool promoteViews);
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void runOnFunction() {
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void runOnFunction() override {
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tileLinalgOps(getFunction(), tileSizes, promoteViews);
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}
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@ -165,7 +165,7 @@ private:
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}
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/// Process member decoration
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LogicalResult processMemberDecoration(uint32_t structID, uint32_t memberNum,
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LogicalResult processMemberDecoration(uint32_t structID, uint32_t memberIndex,
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spirv::Decoration decorationType,
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ArrayRef<uint32_t> values = {});
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@ -1434,7 +1434,7 @@ StringRef OperationPrinter::uniqueValueName(StringRef name) {
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// generates new names by incrementing nextConflictID.
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SmallString<64> probeName(name);
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probeName.push_back('_');
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while (1) {
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while (true) {
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probeName.resize(name.size() + 1);
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probeName += llvm::utostr(nextConflictID++);
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if (!usedNames.count(probeName)) {
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@ -769,7 +769,7 @@ struct ParallelDiagnosticHandlerImpl : public llvm::PrettyStackTraceEntry {
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});
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}
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~ParallelDiagnosticHandlerImpl() {
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~ParallelDiagnosticHandlerImpl() override {
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// Restore the previous diagnostic handler.
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context->getDiagEngine().setHandler(prevHandler);
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@ -369,7 +369,7 @@ Token Lexer::lexPrefixedIdentifier(const char *tokStart) {
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Token Lexer::lexString(const char *tokStart) {
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assert(curPtr[-1] == '"');
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while (1) {
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while (true) {
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switch (*curPtr++) {
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case '"':
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return formToken(Token::string, tokStart);
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@ -4102,7 +4102,7 @@ ParseResult ModuleParser::parseModule(ModuleOp module) {
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// Module itself is a name scope.
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opParser.pushSSANameScope(/*isIsolated=*/true);
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while (1) {
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while (true) {
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switch (getToken().getKind()) {
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default:
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// Parse a top-level operation.
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@ -25,6 +25,7 @@
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#include "mlir/IR/Diagnostics.h"
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#include "mlir/IR/Dialect.h"
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#include "mlir/IR/Module.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Mutex.h"
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#include "llvm/Support/Parallel.h"
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@ -468,7 +469,7 @@ void PassManager::disableMultithreading(bool disable) {
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/// Add the provided instrumentation to the pass manager.
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void PassManager::addInstrumentation(std::unique_ptr<PassInstrumentation> pi) {
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if (!instrumentor)
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instrumentor.reset(new PassInstrumentor());
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instrumentor = std::make_unique<PassInstrumentor>();
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instrumentor->addInstrumentation(std::move(pi));
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}
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@ -18,6 +18,7 @@
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#include "PassDetail.h"
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#include "mlir/Pass/PassManager.h"
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#include "llvm/ADT/MapVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Format.h"
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@ -86,7 +87,7 @@ struct Timer {
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std::function<std::string()> &&nameBuilder) {
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auto &child = children[id];
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if (!child)
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child.reset(new Timer(nameBuilder(), kind));
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child = std::make_unique<Timer>(nameBuilder(), kind);
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return child.get();
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}
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@ -169,7 +170,7 @@ struct Timer {
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struct PassTiming : public PassInstrumentation {
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PassTiming(PassTimingDisplayMode displayMode) : displayMode(displayMode) {}
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~PassTiming() { print(); }
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~PassTiming() override { print(); }
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/// Setup the instrumentation hooks.
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void runBeforePipeline(const OperationName &name,
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@ -222,7 +223,7 @@ struct PassTiming : public PassInstrumentation {
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if (activeTimers.empty()) {
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auto &rootTimer = rootTimers[tid];
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if (!rootTimer)
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rootTimer.reset(new Timer("root", TimerKind::Pipeline));
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rootTimer = std::make_unique<Timer>("root", TimerKind::Pipeline);
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parentTimer = rootTimer.get();
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} else {
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// Otherwise, add this to the active timer.
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@ -43,7 +43,6 @@
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#define DEBUG_TYPE "affine-data-copy-generate"
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using namespace mlir;
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using llvm::SmallMapVector;
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static llvm::cl::OptionCategory clOptionsCategory(DEBUG_TYPE " options");
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@ -381,8 +381,8 @@ class AffineApplyLowering : public OpRewritePattern<AffineApplyOp> {
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public:
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using OpRewritePattern<AffineApplyOp>::OpRewritePattern;
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virtual PatternMatchResult
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matchAndRewrite(AffineApplyOp op, PatternRewriter &rewriter) const override {
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PatternMatchResult matchAndRewrite(AffineApplyOp op,
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PatternRewriter &rewriter) const override {
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auto maybeExpandedMap =
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expandAffineMap(rewriter, op.getLoc(), op.getAffineMap(),
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llvm::to_vector<8>(op.getOperands()));
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@ -400,8 +400,8 @@ class AffineLoadLowering : public OpRewritePattern<AffineLoadOp> {
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public:
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using OpRewritePattern<AffineLoadOp>::OpRewritePattern;
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virtual PatternMatchResult
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matchAndRewrite(AffineLoadOp op, PatternRewriter &rewriter) const override {
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PatternMatchResult matchAndRewrite(AffineLoadOp op,
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PatternRewriter &rewriter) const override {
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// Expand affine map from 'affineLoadOp'.
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SmallVector<Value *, 8> indices(op.getMapOperands());
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auto maybeExpandedMap =
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@ -422,8 +422,8 @@ class AffineStoreLowering : public OpRewritePattern<AffineStoreOp> {
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public:
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using OpRewritePattern<AffineStoreOp>::OpRewritePattern;
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virtual PatternMatchResult
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matchAndRewrite(AffineStoreOp op, PatternRewriter &rewriter) const override {
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PatternMatchResult matchAndRewrite(AffineStoreOp op,
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PatternRewriter &rewriter) const override {
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// Expand affine map from 'affineStoreOp'.
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SmallVector<Value *, 8> indices(op.getMapOperands());
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auto maybeExpandedMap =
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@ -445,9 +445,8 @@ class AffineDmaStartLowering : public OpRewritePattern<AffineDmaStartOp> {
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public:
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using OpRewritePattern<AffineDmaStartOp>::OpRewritePattern;
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virtual PatternMatchResult
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matchAndRewrite(AffineDmaStartOp op,
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PatternRewriter &rewriter) const override {
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PatternMatchResult matchAndRewrite(AffineDmaStartOp op,
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PatternRewriter &rewriter) const override {
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SmallVector<Value *, 8> operands(op.getOperands());
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auto operandsRef = llvm::makeArrayRef(operands);
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@ -486,9 +485,8 @@ class AffineDmaWaitLowering : public OpRewritePattern<AffineDmaWaitOp> {
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public:
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using OpRewritePattern<AffineDmaWaitOp>::OpRewritePattern;
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virtual PatternMatchResult
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matchAndRewrite(AffineDmaWaitOp op,
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PatternRewriter &rewriter) const override {
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PatternMatchResult matchAndRewrite(AffineDmaWaitOp op,
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PatternRewriter &rewriter) const override {
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// Expand affine map for DMA tag memref.
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SmallVector<Value *, 8> indices(op.getTagIndices());
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auto maybeExpandedTagMap =
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@ -361,7 +361,7 @@ VectorTransferRewriter<VectorTransferWriteOp>::matchAndRewrite(
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struct LowerVectorTransfersPass
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: public FunctionPass<LowerVectorTransfersPass> {
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void runOnFunction() {
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void runOnFunction() override {
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OwningRewritePatternList patterns;
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auto *context = &getContext();
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patterns.insert<VectorTransferRewriter<vector::VectorTransferReadOp>,
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@ -42,7 +42,6 @@
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#define DEBUG_TYPE "LoopUtils"
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using namespace mlir;
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using llvm::MapVector;
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using llvm::SetVector;
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using llvm::SmallMapVector;
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@ -74,7 +74,7 @@ struct PrintCFGPass : public FunctionPass<PrintCFGPass> {
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PrintCFGPass(llvm::raw_ostream &os = llvm::errs(), bool shortNames = false,
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const llvm::Twine &title = "")
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: os(os), shortNames(shortNames), title(title.str()) {}
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void runOnFunction() {
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void runOnFunction() override {
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mlir::writeGraph(os, getFunction().getBody(), shortNames, title);
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}
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@ -54,7 +54,7 @@ struct TestInlinerInterface : public DialectInlinerInterface {
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return true;
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}
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bool shouldAnalyzeRecursively(Operation *op) const {
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bool shouldAnalyzeRecursively(Operation *op) const override {
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// Analyze recursively if this is not a functional region operation, it
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// froms a separate functional scope.
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return !isa<FunctionalRegionOp>(op);
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